1201 lines
34 KiB
C
1201 lines
34 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek clock driver for MT7623 SoC
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*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <[email protected]>
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*/
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#include <dm.h>
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#include <log.h>
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#include <asm/arch-mediatek/reset.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/mt7623-clk.h>
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#include <linux/bitops.h>
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#include "clk-mtk.h"
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#define MT7623_CLKSQ_STB_CON0 0x18
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#define MT7623_PLL_ISO_CON0 0x24
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#define MT7623_PLL_FMAX (2000UL * MHZ)
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#define MT7623_CON0_RST_BAR BIT(27)
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#define MCU_AXI_DIV 0x60
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#define AXI_DIV_MSK GENMASK(4, 0)
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#define AXI_DIV_SEL(x) (x)
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/* apmixedsys */
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static const int pll_id_offs_map[] = {
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[CLK_APMIXED_ARMPLL] = 0,
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[CLK_APMIXED_MAINPLL] = 1,
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[CLK_APMIXED_UNIVPLL] = 2,
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[CLK_APMIXED_MMPLL] = 3,
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[CLK_APMIXED_MSDCPLL] = 4,
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[CLK_APMIXED_TVDPLL] = 5,
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[CLK_APMIXED_AUD1PLL] = 6,
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[CLK_APMIXED_TRGPLL] = 7,
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[CLK_APMIXED_ETHPLL] = 8,
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[CLK_APMIXED_VDECPLL] = 9,
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[CLK_APMIXED_HADDS2PLL] = 10,
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[CLK_APMIXED_AUD2PLL] = 11,
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[CLK_APMIXED_TVD2PLL] = 12,
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};
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#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
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_pd_shift, _pcw_reg, _pcw_shift) { \
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.id = _id, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.rst_bar_mask = MT7623_CON0_RST_BAR, \
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.fmax = MT7623_PLL_FMAX, \
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.flags = _flags, \
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.pcwbits = _pcwbits, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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}
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static const struct mtk_pll_data apmixed_plls[] = {
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PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0,
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21, 0x204, 24, 0x204, 0),
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PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR,
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21, 0x210, 4, 0x214, 0),
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PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR,
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7, 0x220, 4, 0x224, 14),
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PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
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21, 0x230, 4, 0x234, 0),
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PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0,
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21, 0x240, 4, 0x244, 0),
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PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x00000001, 0,
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21, 0x250, 4, 0x254, 0),
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PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x00000001, 0,
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31, 0x270, 4, 0x274, 0),
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PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0,
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31, 0x280, 4, 0x284, 0),
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PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x00000001, 0,
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31, 0x290, 4, 0x294, 0),
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PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x00000001, 0,
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31, 0x2a0, 4, 0x2a4, 0),
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PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x00000001, 0,
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31, 0x2b0, 4, 0x2b4, 0),
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PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x00000001, 0,
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31, 0x2c0, 4, 0x2c4, 0),
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PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x00000001, 0,
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21, 0x2d0, 4, 0x2d4, 0),
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};
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/* topckgen */
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/* Fixed CLK exposed upstream by the hdmi PHY driver */
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#define CLK_TOP_HDMITX_CLKDIG_CTS CLK_TOP_NR
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static const int top_id_offs_map[CLK_TOP_NR + 1] = {
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/* Fixed CLK */
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[CLK_TOP_DPI] = 0,
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[CLK_TOP_DMPLL] = 1,
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[CLK_TOP_VENCPLL] = 2,
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[CLK_TOP_HDMI_0_PIX340M] = 3,
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[CLK_TOP_HDMI_0_DEEP340M] = 4,
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[CLK_TOP_HDMI_0_PLL340M] = 5,
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[CLK_TOP_HADDS2_FB] = 6,
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[CLK_TOP_WBG_DIG_416M] = 7,
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[CLK_TOP_DSI0_LNTC_DSI] = 8,
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[CLK_TOP_HDMI_SCL_RX] = 9,
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[CLK_TOP_32K_EXTERNAL] = 10,
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[CLK_TOP_HDMITX_CLKDIG_CTS] = 11,
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[CLK_TOP_AUD_EXT1] = 12,
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[CLK_TOP_AUD_EXT2] = 13,
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[CLK_TOP_NFI1X_PAD] = 14,
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/* Factor CLK */
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[CLK_TOP_SYSPLL] = 15,
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[CLK_TOP_SYSPLL_D2] = 16,
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[CLK_TOP_SYSPLL_D3] = 17,
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[CLK_TOP_SYSPLL_D5] = 18,
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[CLK_TOP_SYSPLL_D7] = 19,
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[CLK_TOP_SYSPLL1_D2] = 20,
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[CLK_TOP_SYSPLL1_D4] = 21,
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[CLK_TOP_SYSPLL1_D8] = 22,
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[CLK_TOP_SYSPLL1_D16] = 23,
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[CLK_TOP_SYSPLL2_D2] = 24,
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[CLK_TOP_SYSPLL2_D4] = 25,
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[CLK_TOP_SYSPLL2_D8] = 26,
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[CLK_TOP_SYSPLL3_D2] = 27,
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[CLK_TOP_SYSPLL3_D4] = 28,
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[CLK_TOP_SYSPLL4_D2] = 29,
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[CLK_TOP_SYSPLL4_D4] = 30,
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[CLK_TOP_UNIVPLL] = 31,
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[CLK_TOP_UNIVPLL_D2] = 32,
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[CLK_TOP_UNIVPLL_D3] = 33,
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[CLK_TOP_UNIVPLL_D5] = 34,
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[CLK_TOP_UNIVPLL_D7] = 35,
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[CLK_TOP_UNIVPLL_D26] = 36,
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[CLK_TOP_UNIVPLL_D52] = 37,
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[CLK_TOP_UNIVPLL_D108] = 38,
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[CLK_TOP_USB_PHY48M] = 39,
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[CLK_TOP_UNIVPLL1_D2] = 40,
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[CLK_TOP_UNIVPLL1_D4] = 41,
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[CLK_TOP_UNIVPLL1_D8] = 42,
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[CLK_TOP_UNIVPLL2_D2] = 43,
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[CLK_TOP_UNIVPLL2_D4] = 44,
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[CLK_TOP_UNIVPLL2_D8] = 45,
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[CLK_TOP_UNIVPLL2_D16] = 46,
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[CLK_TOP_UNIVPLL2_D32] = 47,
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[CLK_TOP_UNIVPLL3_D2] = 48,
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[CLK_TOP_UNIVPLL3_D4] = 49,
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[CLK_TOP_UNIVPLL3_D8] = 50,
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[CLK_TOP_MSDCPLL] = 51,
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[CLK_TOP_MSDCPLL_D2] = 52,
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[CLK_TOP_MSDCPLL_D4] = 53,
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[CLK_TOP_MSDCPLL_D8] = 54,
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[CLK_TOP_MMPLL] = 55,
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[CLK_TOP_MMPLL_D2] = 56,
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[CLK_TOP_DMPLL_D2] = 57,
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[CLK_TOP_DMPLL_D4] = 58,
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[CLK_TOP_DMPLL_X2] = 59,
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[CLK_TOP_TVDPLL] = 60,
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[CLK_TOP_TVDPLL_D2] = 61,
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[CLK_TOP_TVDPLL_D4] = 62,
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[CLK_TOP_VDECPLL] = 63,
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[CLK_TOP_TVD2PLL] = 64,
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[CLK_TOP_TVD2PLL_D2] = 65,
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[CLK_TOP_MIPIPLL] = 66,
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[CLK_TOP_MIPIPLL_D2] = 67,
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[CLK_TOP_MIPIPLL_D4] = 68,
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[CLK_TOP_HDMIPLL] = 69,
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[CLK_TOP_HDMIPLL_D2] = 70,
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[CLK_TOP_HDMIPLL_D3] = 71,
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[CLK_TOP_ARMPLL_1P3G] = 72,
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[CLK_TOP_AUDPLL] = 73,
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[CLK_TOP_AUDPLL_D4] = 74,
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[CLK_TOP_AUDPLL_D8] = 75,
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[CLK_TOP_AUDPLL_D16] = 76,
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[CLK_TOP_AUDPLL_D24] = 77,
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[CLK_TOP_AUD1PLL_98M] = 78,
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[CLK_TOP_AUD2PLL_90M] = 79,
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[CLK_TOP_HADDS2PLL_98M] = 80,
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[CLK_TOP_HADDS2PLL_294M] = 81,
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[CLK_TOP_ETHPLL_500M] = 82,
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[CLK_TOP_CLK26M_D8] = 83,
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[CLK_TOP_32K_INTERNAL] = 84,
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[CLK_TOP_AXISEL_D4] = 85,
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[CLK_TOP_8BDAC] = 86,
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/* MUX CLK */
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[CLK_TOP_AXI_SEL] = 87,
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[CLK_TOP_MEM_SEL] = 88,
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[CLK_TOP_DDRPHYCFG_SEL] = 89,
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[CLK_TOP_MM_SEL] = 90,
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[CLK_TOP_PWM_SEL] = 91,
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[CLK_TOP_VDEC_SEL] = 92,
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[CLK_TOP_MFG_SEL] = 93,
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[CLK_TOP_CAMTG_SEL] = 94,
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[CLK_TOP_UART_SEL] = 95,
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[CLK_TOP_SPI0_SEL] = 96,
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[CLK_TOP_USB20_SEL] = 97,
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[CLK_TOP_MSDC30_0_SEL] = 98,
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[CLK_TOP_MSDC30_1_SEL] = 99,
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[CLK_TOP_MSDC30_2_SEL] = 100,
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[CLK_TOP_AUDIO_SEL] = 101,
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[CLK_TOP_AUDINTBUS_SEL] = 102,
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[CLK_TOP_PMICSPI_SEL] = 103,
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[CLK_TOP_SCP_SEL] = 104,
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[CLK_TOP_DPI0_SEL] = 105,
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[CLK_TOP_DPI1_SEL] = 106,
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[CLK_TOP_TVE_SEL] = 107,
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[CLK_TOP_HDMI_SEL] = 108,
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[CLK_TOP_APLL_SEL] = 109,
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[CLK_TOP_RTC_SEL] = 110,
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[CLK_TOP_NFI2X_SEL] = 111,
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[CLK_TOP_EMMC_HCLK_SEL] = 112,
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[CLK_TOP_FLASH_SEL] = 113,
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[CLK_TOP_DI_SEL] = 114,
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[CLK_TOP_NR_SEL] = 115,
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[CLK_TOP_OSD_SEL] = 116,
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[CLK_TOP_HDMIRX_BIST_SEL] = 117,
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[CLK_TOP_INTDIR_SEL] = 118,
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[CLK_TOP_ASM_I_SEL] = 119,
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[CLK_TOP_ASM_M_SEL] = 120,
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[CLK_TOP_ASM_H_SEL] = 121,
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[CLK_TOP_MS_CARD_SEL] = 122,
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[CLK_TOP_ETHIF_SEL] = 123,
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[CLK_TOP_HDMIRX26_24_SEL] = 124,
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[CLK_TOP_MSDC30_3_SEL] = 125,
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[CLK_TOP_CMSYS_SEL] = 126,
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[CLK_TOP_SPI1_SEL] = 127,
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[CLK_TOP_SPI2_SEL] = 128,
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[CLK_TOP_8BDAC_SEL] = 129,
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[CLK_TOP_AUD2DVD_SEL] = 130,
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[CLK_TOP_PADMCLK_SEL] = 131,
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[CLK_TOP_AUD_MUX1_SEL] = 132,
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[CLK_TOP_AUD_MUX2_SEL] = 133,
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[CLK_TOP_AUDPLL_MUX_SEL] = 134,
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[CLK_TOP_AUD_K1_SRC_SEL] = 135,
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[CLK_TOP_AUD_K2_SRC_SEL] = 136,
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[CLK_TOP_AUD_K3_SRC_SEL] = 137,
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[CLK_TOP_AUD_K4_SRC_SEL] = 138,
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[CLK_TOP_AUD_K5_SRC_SEL] = 139,
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[CLK_TOP_AUD_K6_SRC_SEL] = 140,
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/* Misc CLK only used as parents */
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[CLK_TOP_AUD_EXTCK1_DIV] = 141,
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[CLK_TOP_AUD_EXTCK2_DIV] = 142,
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[CLK_TOP_AUD_MUX1_DIV] = 143,
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[CLK_TOP_AUD_MUX2_DIV] = 144,
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[CLK_TOP_AUD_K1_SRC_DIV] = 145,
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[CLK_TOP_AUD_K2_SRC_DIV] = 146,
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[CLK_TOP_AUD_K3_SRC_DIV] = 147,
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[CLK_TOP_AUD_K4_SRC_DIV] = 148,
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[CLK_TOP_AUD_K5_SRC_DIV] = 149,
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[CLK_TOP_AUD_K6_SRC_DIV] = 150,
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[CLK_TOP_AUD_48K_TIMING] = 151,
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[CLK_TOP_AUD_44K_TIMING] = 152,
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[CLK_TOP_AUD_I2S1_MCLK] = 153,
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[CLK_TOP_AUD_I2S2_MCLK] = 154,
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[CLK_TOP_AUD_I2S3_MCLK] = 155,
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[CLK_TOP_AUD_I2S4_MCLK] = 156,
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[CLK_TOP_AUD_I2S5_MCLK] = 157,
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[CLK_TOP_AUD_I2S6_MCLK] = 158,
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};
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#define FACTOR0(_id, _parent, _mult, _div) \
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FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
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#define FACTOR1(_id, _parent, _mult, _div) \
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FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
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#define FACTOR2(_id, _parent, _mult, _div) \
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FACTOR(_id, _parent, _mult, _div, 0)
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static const struct mtk_fixed_clk top_fixed_clks[] = {
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FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
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FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
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FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
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FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
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FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
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FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
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FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
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FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
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FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
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FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ),
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FIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000),
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FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, CLK_XTAL, 300 * MHZ),
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FIXED_CLK(CLK_TOP_AUD_EXT1, CLK_XTAL, 0),
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FIXED_CLK(CLK_TOP_AUD_EXT2, CLK_XTAL, 0),
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FIXED_CLK(CLK_TOP_NFI1X_PAD, CLK_XTAL, 0),
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};
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static const struct mtk_fixed_factor top_fixed_divs[] = {
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FACTOR0(CLK_TOP_SYSPLL, CLK_APMIXED_MAINPLL, 1, 1),
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FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
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FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
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FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
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FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
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FACTOR1(CLK_TOP_SYSPLL1_D2, CLK_TOP_SYSPLL_D2, 1, 2),
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FACTOR1(CLK_TOP_SYSPLL1_D4, CLK_TOP_SYSPLL_D2, 1, 4),
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FACTOR1(CLK_TOP_SYSPLL1_D8, CLK_TOP_SYSPLL_D2, 1, 8),
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FACTOR1(CLK_TOP_SYSPLL1_D16, CLK_TOP_SYSPLL_D2, 1, 16),
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FACTOR1(CLK_TOP_SYSPLL2_D2, CLK_TOP_SYSPLL_D3, 1, 2),
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FACTOR1(CLK_TOP_SYSPLL2_D4, CLK_TOP_SYSPLL_D3, 1, 4),
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FACTOR1(CLK_TOP_SYSPLL2_D8, CLK_TOP_SYSPLL_D3, 1, 8),
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FACTOR1(CLK_TOP_SYSPLL3_D2, CLK_TOP_SYSPLL_D5, 1, 2),
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FACTOR1(CLK_TOP_SYSPLL3_D4, CLK_TOP_SYSPLL_D5, 1, 4),
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FACTOR1(CLK_TOP_SYSPLL4_D2, CLK_TOP_SYSPLL_D7, 1, 2),
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FACTOR1(CLK_TOP_SYSPLL4_D4, CLK_TOP_SYSPLL_D7, 1, 4),
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FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 1),
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FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
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FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
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FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
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FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7),
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FACTOR0(CLK_TOP_UNIVPLL_D26, CLK_APMIXED_UNIVPLL, 1, 26),
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FACTOR0(CLK_TOP_UNIVPLL_D52, CLK_APMIXED_UNIVPLL, 1, 52),
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FACTOR0(CLK_TOP_UNIVPLL_D108, CLK_APMIXED_UNIVPLL, 1, 108),
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FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
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FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL_D2, 1, 2),
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FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL_D2, 1, 4),
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FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL_D2, 1, 8),
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FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL_D3, 1, 2),
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FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL_D3, 1, 4),
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FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL_D3, 1, 8),
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FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL_D3, 1, 16),
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FACTOR1(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL_D3, 1, 32),
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FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL_D5, 1, 2),
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FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL_D5, 1, 4),
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FACTOR1(CLK_TOP_UNIVPLL3_D8, CLK_TOP_UNIVPLL_D5, 1, 8),
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FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
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FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
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FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4),
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FACTOR0(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1, 8),
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FACTOR0(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1),
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FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
|
|
|
|
FACTOR1(CLK_TOP_DMPLL_D2, CLK_TOP_DMPLL, 1, 2),
|
|
FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_DMPLL, 1, 4),
|
|
FACTOR1(CLK_TOP_DMPLL_X2, CLK_TOP_DMPLL, 1, 1),
|
|
|
|
FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
|
|
FACTOR0(CLK_TOP_TVDPLL_D2, CLK_APMIXED_TVDPLL, 1, 2),
|
|
FACTOR0(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4),
|
|
|
|
FACTOR0(CLK_TOP_VDECPLL, CLK_APMIXED_VDECPLL, 1, 1),
|
|
FACTOR0(CLK_TOP_TVD2PLL, CLK_APMIXED_TVD2PLL, 1, 1),
|
|
FACTOR0(CLK_TOP_TVD2PLL_D2, CLK_APMIXED_TVD2PLL, 1, 2),
|
|
|
|
FACTOR1(CLK_TOP_MIPIPLL, CLK_TOP_DPI, 1, 1),
|
|
FACTOR1(CLK_TOP_MIPIPLL_D2, CLK_TOP_DPI, 1, 2),
|
|
FACTOR1(CLK_TOP_MIPIPLL_D4, CLK_TOP_DPI, 1, 4),
|
|
|
|
FACTOR1(CLK_TOP_HDMIPLL, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 1),
|
|
FACTOR1(CLK_TOP_HDMIPLL_D2, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 2),
|
|
FACTOR1(CLK_TOP_HDMIPLL_D3, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 3),
|
|
|
|
FACTOR0(CLK_TOP_ARMPLL_1P3G, CLK_APMIXED_ARMPLL, 1, 1),
|
|
|
|
FACTOR1(CLK_TOP_AUDPLL, CLK_TOP_AUDPLL_MUX_SEL, 1, 1),
|
|
FACTOR1(CLK_TOP_AUDPLL_D4, CLK_TOP_AUDPLL_MUX_SEL, 1, 4),
|
|
FACTOR1(CLK_TOP_AUDPLL_D8, CLK_TOP_AUDPLL_MUX_SEL, 1, 8),
|
|
FACTOR1(CLK_TOP_AUDPLL_D16, CLK_TOP_AUDPLL_MUX_SEL, 1, 16),
|
|
FACTOR1(CLK_TOP_AUDPLL_D24, CLK_TOP_AUDPLL_MUX_SEL, 1, 24),
|
|
|
|
FACTOR0(CLK_TOP_AUD1PLL_98M, CLK_APMIXED_AUD1PLL, 1, 3),
|
|
FACTOR0(CLK_TOP_AUD2PLL_90M, CLK_APMIXED_AUD2PLL, 1, 3),
|
|
FACTOR0(CLK_TOP_HADDS2PLL_98M, CLK_APMIXED_HADDS2PLL, 1, 3),
|
|
FACTOR0(CLK_TOP_HADDS2PLL_294M, CLK_APMIXED_HADDS2PLL, 1, 1),
|
|
FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1),
|
|
FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
|
|
FACTOR2(CLK_TOP_32K_INTERNAL, CLK_XTAL, 1, 793),
|
|
FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4),
|
|
FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1),
|
|
};
|
|
|
|
static const int axi_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL1_D2,
|
|
CLK_TOP_SYSPLL_D5,
|
|
CLK_TOP_SYSPLL1_D4,
|
|
CLK_TOP_UNIVPLL_D5,
|
|
CLK_TOP_UNIVPLL2_D2,
|
|
CLK_TOP_MMPLL_D2,
|
|
CLK_TOP_DMPLL_D2
|
|
};
|
|
|
|
static const int mem_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_DMPLL
|
|
};
|
|
|
|
static const int ddrphycfg_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL1_D8
|
|
};
|
|
|
|
static const int mm_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_VENCPLL,
|
|
CLK_TOP_SYSPLL1_D2,
|
|
CLK_TOP_SYSPLL1_D4,
|
|
CLK_TOP_UNIVPLL_D5,
|
|
CLK_TOP_UNIVPLL1_D2,
|
|
CLK_TOP_UNIVPLL2_D2,
|
|
CLK_TOP_DMPLL
|
|
};
|
|
|
|
static const int pwm_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_UNIVPLL2_D4,
|
|
CLK_TOP_UNIVPLL3_D2,
|
|
CLK_TOP_UNIVPLL1_D4
|
|
};
|
|
|
|
static const int vdec_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_VDECPLL,
|
|
CLK_TOP_SYSPLL_D5,
|
|
CLK_TOP_SYSPLL1_D4,
|
|
CLK_TOP_UNIVPLL_D5,
|
|
CLK_TOP_UNIVPLL2_D2,
|
|
CLK_TOP_VENCPLL,
|
|
CLK_TOP_MSDCPLL_D2,
|
|
CLK_TOP_MMPLL_D2
|
|
};
|
|
|
|
static const int mfg_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_MMPLL,
|
|
CLK_TOP_DMPLL_X2,
|
|
CLK_TOP_MSDCPLL,
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL_D3,
|
|
CLK_TOP_UNIVPLL_D3,
|
|
CLK_TOP_UNIVPLL1_D2
|
|
};
|
|
|
|
static const int camtg_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_UNIVPLL_D26,
|
|
CLK_TOP_UNIVPLL2_D2,
|
|
CLK_TOP_SYSPLL3_D2,
|
|
CLK_TOP_SYSPLL3_D4,
|
|
CLK_TOP_MSDCPLL_D2,
|
|
CLK_TOP_MMPLL_D2
|
|
};
|
|
|
|
static const int uart_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_UNIVPLL2_D8
|
|
};
|
|
|
|
static const int spi_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL3_D2,
|
|
CLK_TOP_SYSPLL4_D2,
|
|
CLK_TOP_UNIVPLL2_D4,
|
|
CLK_TOP_UNIVPLL1_D8
|
|
};
|
|
|
|
static const int usb20_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_UNIVPLL1_D8,
|
|
CLK_TOP_UNIVPLL3_D4
|
|
};
|
|
|
|
static const int msdc30_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_MSDCPLL_D2,
|
|
CLK_TOP_SYSPLL2_D2,
|
|
CLK_TOP_SYSPLL1_D4,
|
|
CLK_TOP_UNIVPLL1_D4,
|
|
CLK_TOP_UNIVPLL2_D4,
|
|
};
|
|
|
|
static const int aud_intbus_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL1_D4,
|
|
CLK_TOP_SYSPLL3_D2,
|
|
CLK_TOP_SYSPLL4_D2,
|
|
CLK_TOP_UNIVPLL3_D2,
|
|
CLK_TOP_UNIVPLL2_D4
|
|
};
|
|
|
|
static const int pmicspi_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL1_D8,
|
|
CLK_TOP_SYSPLL2_D4,
|
|
CLK_TOP_SYSPLL4_D2,
|
|
CLK_TOP_SYSPLL3_D4,
|
|
CLK_TOP_SYSPLL2_D8,
|
|
CLK_TOP_SYSPLL1_D16,
|
|
CLK_TOP_UNIVPLL3_D4,
|
|
CLK_TOP_UNIVPLL_D26,
|
|
CLK_TOP_DMPLL_D2,
|
|
CLK_TOP_DMPLL_D4
|
|
};
|
|
|
|
static const int scp_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL1_D8,
|
|
CLK_TOP_DMPLL_D2,
|
|
CLK_TOP_DMPLL_D4
|
|
};
|
|
|
|
static const int dpi0_tve_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_MIPIPLL,
|
|
CLK_TOP_MIPIPLL_D2,
|
|
CLK_TOP_MIPIPLL_D4,
|
|
CLK_XTAL,
|
|
CLK_TOP_TVDPLL,
|
|
CLK_TOP_TVDPLL_D2,
|
|
CLK_TOP_TVDPLL_D4
|
|
};
|
|
|
|
static const int dpi1_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_TVDPLL,
|
|
CLK_TOP_TVDPLL_D2,
|
|
CLK_TOP_TVDPLL_D4
|
|
};
|
|
|
|
static const int hdmi_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_HDMIPLL,
|
|
CLK_TOP_HDMIPLL_D2,
|
|
CLK_TOP_HDMIPLL_D3
|
|
};
|
|
|
|
static const int apll_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_AUDPLL,
|
|
CLK_TOP_AUDPLL_D4,
|
|
CLK_TOP_AUDPLL_D8,
|
|
CLK_TOP_AUDPLL_D16,
|
|
CLK_TOP_AUDPLL_D24,
|
|
CLK_XTAL,
|
|
CLK_XTAL
|
|
};
|
|
|
|
static const int rtc_parents[] = {
|
|
CLK_TOP_32K_INTERNAL,
|
|
CLK_TOP_32K_EXTERNAL,
|
|
CLK_XTAL,
|
|
CLK_TOP_UNIVPLL3_D8
|
|
};
|
|
|
|
static const int nfi2x_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL2_D2,
|
|
CLK_TOP_SYSPLL_D7,
|
|
CLK_TOP_UNIVPLL3_D2,
|
|
CLK_TOP_SYSPLL2_D4,
|
|
CLK_TOP_UNIVPLL3_D4,
|
|
CLK_TOP_SYSPLL4_D4,
|
|
CLK_XTAL
|
|
};
|
|
|
|
static const int emmc_hclk_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL1_D2,
|
|
CLK_TOP_SYSPLL1_D4,
|
|
CLK_TOP_SYSPLL2_D2
|
|
};
|
|
|
|
static const int flash_parents[] = {
|
|
CLK_TOP_CLK26M_D8,
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL2_D8,
|
|
CLK_TOP_SYSPLL3_D4,
|
|
CLK_TOP_UNIVPLL3_D4,
|
|
CLK_TOP_SYSPLL4_D2,
|
|
CLK_TOP_SYSPLL2_D4,
|
|
CLK_TOP_UNIVPLL2_D4
|
|
};
|
|
|
|
static const int di_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_TVD2PLL,
|
|
CLK_TOP_TVD2PLL_D2,
|
|
CLK_XTAL
|
|
};
|
|
|
|
static const int nr_osd_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_VENCPLL,
|
|
CLK_TOP_SYSPLL1_D2,
|
|
CLK_TOP_SYSPLL1_D4,
|
|
CLK_TOP_UNIVPLL_D5,
|
|
CLK_TOP_UNIVPLL1_D2,
|
|
CLK_TOP_UNIVPLL2_D2,
|
|
CLK_TOP_DMPLL
|
|
};
|
|
|
|
static const int hdmirx_bist_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL_D3,
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL1_D16,
|
|
CLK_TOP_SYSPLL4_D2,
|
|
CLK_TOP_SYSPLL1_D4,
|
|
CLK_TOP_VENCPLL,
|
|
CLK_XTAL
|
|
};
|
|
|
|
static const int intdir_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_MMPLL,
|
|
CLK_TOP_SYSPLL_D2,
|
|
CLK_TOP_UNIVPLL_D2
|
|
};
|
|
|
|
static const int asm_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_UNIVPLL2_D4,
|
|
CLK_TOP_UNIVPLL2_D2,
|
|
CLK_TOP_SYSPLL_D5
|
|
};
|
|
|
|
static const int ms_card_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_UNIVPLL3_D8,
|
|
CLK_TOP_SYSPLL4_D4
|
|
};
|
|
|
|
static const int ethif_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL1_D2,
|
|
CLK_TOP_SYSPLL_D5,
|
|
CLK_TOP_SYSPLL1_D4,
|
|
CLK_TOP_UNIVPLL_D5,
|
|
CLK_TOP_UNIVPLL1_D2,
|
|
CLK_TOP_DMPLL,
|
|
CLK_TOP_DMPLL_D2
|
|
};
|
|
|
|
static const int hdmirx_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_UNIVPLL_D52
|
|
};
|
|
|
|
static const int cmsys_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_SYSPLL1_D2,
|
|
CLK_TOP_UNIVPLL1_D2,
|
|
CLK_TOP_UNIVPLL_D5,
|
|
CLK_TOP_SYSPLL_D5,
|
|
CLK_TOP_SYSPLL2_D2,
|
|
CLK_TOP_SYSPLL1_D4,
|
|
CLK_TOP_SYSPLL3_D2,
|
|
CLK_TOP_SYSPLL2_D4,
|
|
CLK_TOP_SYSPLL1_D8,
|
|
CLK_XTAL,
|
|
CLK_XTAL,
|
|
CLK_XTAL,
|
|
CLK_XTAL,
|
|
CLK_XTAL
|
|
};
|
|
|
|
static const int clk_8bdac_parents[] = {
|
|
CLK_TOP_32K_INTERNAL,
|
|
CLK_TOP_8BDAC,
|
|
CLK_XTAL,
|
|
CLK_XTAL
|
|
};
|
|
|
|
static const int aud2dvd_parents[] = {
|
|
CLK_TOP_AUD_48K_TIMING,
|
|
CLK_TOP_AUD_44K_TIMING
|
|
};
|
|
|
|
static const int padmclk_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_UNIVPLL_D26,
|
|
CLK_TOP_UNIVPLL_D52,
|
|
CLK_TOP_UNIVPLL_D108,
|
|
CLK_TOP_UNIVPLL2_D8,
|
|
CLK_TOP_UNIVPLL2_D16,
|
|
CLK_TOP_UNIVPLL2_D32
|
|
};
|
|
|
|
static const int aud_mux_parents[] = {
|
|
CLK_XTAL,
|
|
CLK_TOP_AUD1PLL_98M,
|
|
CLK_TOP_AUD2PLL_90M,
|
|
CLK_TOP_HADDS2PLL_98M,
|
|
CLK_TOP_AUD_EXTCK1_DIV,
|
|
CLK_TOP_AUD_EXTCK2_DIV
|
|
};
|
|
|
|
static const int aud_src_parents[] = {
|
|
CLK_TOP_AUD_MUX1_SEL,
|
|
CLK_TOP_AUD_MUX2_SEL
|
|
};
|
|
|
|
static const struct mtk_composite top_muxes[] = {
|
|
MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
|
|
MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
|
|
MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
|
|
MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31,
|
|
CLK_DOMAIN_SCPSYS),
|
|
|
|
MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
|
|
MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15),
|
|
MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23,
|
|
CLK_DOMAIN_SCPSYS),
|
|
MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31),
|
|
|
|
MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
|
|
MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15),
|
|
MUX_GATE(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23),
|
|
MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31),
|
|
|
|
MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7),
|
|
MUX_GATE(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15),
|
|
MUX_GATE(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23),
|
|
MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31),
|
|
|
|
MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7),
|
|
MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15),
|
|
MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23),
|
|
MUX_GATE(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31),
|
|
|
|
MUX_GATE(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7),
|
|
MUX_GATE(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15),
|
|
MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
|
|
|
|
MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7),
|
|
MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15),
|
|
MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31),
|
|
|
|
MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7),
|
|
MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15),
|
|
MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23),
|
|
MUX_GATE(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31),
|
|
|
|
MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7),
|
|
MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15),
|
|
MUX_GATE(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23),
|
|
MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31),
|
|
|
|
MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7),
|
|
MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23),
|
|
MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31,
|
|
CLK_DOMAIN_SCPSYS),
|
|
|
|
MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7),
|
|
MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15),
|
|
MUX_GATE(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23),
|
|
|
|
MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31),
|
|
MUX_GATE(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7),
|
|
MUX_GATE(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15),
|
|
MUX_GATE(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23),
|
|
|
|
MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3),
|
|
|
|
MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3),
|
|
MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3),
|
|
MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3),
|
|
|
|
MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23),
|
|
MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24),
|
|
MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25),
|
|
MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26),
|
|
MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27),
|
|
MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28),
|
|
};
|
|
|
|
/* infracfg */
|
|
static const struct mtk_gate_regs infra_cg_regs = {
|
|
.set_ofs = 0x40,
|
|
.clr_ofs = 0x44,
|
|
.sta_ofs = 0x48,
|
|
};
|
|
|
|
#define GATE_INFRA_FLAGS(_id, _parent, _shift, _flags) { \
|
|
.id = _id, \
|
|
.parent = _parent, \
|
|
.regs = &infra_cg_regs, \
|
|
.shift = _shift, \
|
|
.flags = _flags, \
|
|
}
|
|
#define GATE_INFRA(_id, _parent, _shift) \
|
|
GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
|
|
#define GATE_INFRA_XTAL(_id, _parent, _shift) \
|
|
GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
|
|
|
|
|
|
static const struct mtk_gate infra_cgs[] = {
|
|
GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
|
|
GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1),
|
|
GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2),
|
|
GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4),
|
|
GATE_INFRA_XTAL(CLK_INFRA_AUDIO, CLK_XTAL, 5),
|
|
GATE_INFRA_XTAL(CLK_INFRA_EFUSE, CLK_XTAL, 6),
|
|
GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7),
|
|
GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8),
|
|
GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12),
|
|
GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 13),
|
|
GATE_INFRA(CLK_INFRA_RAMBUFIF, CLK_TOP_MEM_SEL, 14),
|
|
GATE_INFRA(CLK_INFRA_CPUM, CLK_TOP_MEM_SEL, 15),
|
|
GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16),
|
|
GATE_INFRA(CLK_INFRA_CEC, CLK_TOP_RTC_SEL, 18),
|
|
GATE_INFRA(CLK_INFRA_IRRX, CLK_TOP_AXI_SEL, 19),
|
|
GATE_INFRA(CLK_INFRA_PMICSPI, CLK_TOP_PMICSPI_SEL, 22),
|
|
GATE_INFRA(CLK_INFRA_PMICWRAP, CLK_TOP_AXI_SEL, 23),
|
|
GATE_INFRA(CLK_INFRA_DDCCI, CLK_TOP_AXI_SEL, 24),
|
|
};
|
|
|
|
/* pericfg */
|
|
static const int peri_id_offs_map[] = {
|
|
/* MUX CLK */
|
|
[CLK_PERI_UART0_SEL] = 1,
|
|
[CLK_PERI_UART1_SEL] = 2,
|
|
[CLK_PERI_UART2_SEL] = 3,
|
|
[CLK_PERI_UART3_SEL] = 4,
|
|
/* GATE CLK */
|
|
[CLK_PERI_NFI] = 5,
|
|
[CLK_PERI_THERM] = 6,
|
|
[CLK_PERI_PWM1] = 7,
|
|
[CLK_PERI_PWM2] = 8,
|
|
[CLK_PERI_PWM3] = 9,
|
|
[CLK_PERI_PWM4] = 10,
|
|
[CLK_PERI_PWM5] = 11,
|
|
[CLK_PERI_PWM6] = 12,
|
|
[CLK_PERI_PWM7] = 13,
|
|
[CLK_PERI_PWM] = 14,
|
|
[CLK_PERI_USB0] = 15,
|
|
[CLK_PERI_USB1] = 16,
|
|
[CLK_PERI_AP_DMA] = 17,
|
|
[CLK_PERI_MSDC30_0] = 18,
|
|
[CLK_PERI_MSDC30_1] = 19,
|
|
[CLK_PERI_MSDC30_2] = 20,
|
|
[CLK_PERI_MSDC30_3] = 21,
|
|
[CLK_PERI_MSDC50_3] = 22,
|
|
[CLK_PERI_NLI] = 23,
|
|
[CLK_PERI_UART0] = 24,
|
|
[CLK_PERI_UART1] = 25,
|
|
[CLK_PERI_UART2] = 26,
|
|
[CLK_PERI_UART3] = 27,
|
|
[CLK_PERI_BTIF] = 28,
|
|
[CLK_PERI_I2C0] = 29,
|
|
[CLK_PERI_I2C1] = 30,
|
|
[CLK_PERI_I2C2] = 31,
|
|
[CLK_PERI_I2C3] = 32,
|
|
[CLK_PERI_AUXADC] = 33,
|
|
[CLK_PERI_SPI0] = 34,
|
|
[CLK_PERI_ETH] = 35,
|
|
[CLK_PERI_USB0_MCU] = 36,
|
|
[CLK_PERI_USB1_MCU] = 37,
|
|
[CLK_PERI_USB_SLV] = 38,
|
|
[CLK_PERI_GCPU] = 39,
|
|
[CLK_PERI_NFI_ECC] = 40,
|
|
[CLK_PERI_NFI_PAD] = 41,
|
|
[CLK_PERI_FLASH] = 42,
|
|
[CLK_PERI_HOST89_INT] = 43,
|
|
[CLK_PERI_HOST89_SPI] = 44,
|
|
[CLK_PERI_HOST89_DVD] = 45,
|
|
[CLK_PERI_SPI1] = 46,
|
|
[CLK_PERI_SPI2] = 47,
|
|
[CLK_PERI_FCI] = 48,
|
|
};
|
|
|
|
#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
|
|
#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL)
|
|
|
|
static const struct mtk_parent uart_ck_sel_parents[] = {
|
|
XTAL_PARENT(CLK_XTAL),
|
|
TOP_PARENT(CLK_TOP_UART_SEL),
|
|
};
|
|
|
|
static const struct mtk_composite peri_muxes[] = {
|
|
MUX_MIXED(CLK_PERI_UART0_SEL, uart_ck_sel_parents, 0x40C, 0, 1),
|
|
MUX_MIXED(CLK_PERI_UART1_SEL, uart_ck_sel_parents, 0x40C, 1, 1),
|
|
MUX_MIXED(CLK_PERI_UART2_SEL, uart_ck_sel_parents, 0x40C, 2, 1),
|
|
MUX_MIXED(CLK_PERI_UART3_SEL, uart_ck_sel_parents, 0x40C, 3, 1),
|
|
};
|
|
|
|
static const struct mtk_gate_regs peri0_cg_regs = {
|
|
.set_ofs = 0x8,
|
|
.clr_ofs = 0x10,
|
|
.sta_ofs = 0x18,
|
|
};
|
|
|
|
static const struct mtk_gate_regs peri1_cg_regs = {
|
|
.set_ofs = 0xC,
|
|
.clr_ofs = 0x14,
|
|
.sta_ofs = 0x1C,
|
|
};
|
|
|
|
#define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) { \
|
|
.id = _id, \
|
|
.parent = _parent, \
|
|
.regs = &peri0_cg_regs, \
|
|
.shift = _shift, \
|
|
.flags = _flags, \
|
|
}
|
|
#define GATE_PERI0(_id, _parent, _shift) \
|
|
GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
|
|
#define GATE_PERI0_XTAL(_id, _parent, _shift) \
|
|
GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
|
|
|
|
#define GATE_PERI1(_id, _parent, _shift) { \
|
|
.id = _id, \
|
|
.parent = _parent, \
|
|
.regs = &peri1_cg_regs, \
|
|
.shift = _shift, \
|
|
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
|
|
}
|
|
|
|
static const struct mtk_gate peri_cgs[] = {
|
|
GATE_PERI0(CLK_PERI_NFI, CLK_TOP_NFI2X_SEL, 0),
|
|
GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1),
|
|
GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2),
|
|
GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3),
|
|
GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4),
|
|
GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5),
|
|
GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6),
|
|
GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7),
|
|
GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8),
|
|
GATE_PERI0(CLK_PERI_PWM, CLK_TOP_AXI_SEL, 9),
|
|
GATE_PERI0(CLK_PERI_USB0, CLK_TOP_USB20_SEL, 10),
|
|
GATE_PERI0(CLK_PERI_USB1, CLK_TOP_USB20_SEL, 11),
|
|
GATE_PERI0(CLK_PERI_AP_DMA, CLK_TOP_AXI_SEL, 12),
|
|
GATE_PERI0(CLK_PERI_MSDC30_0, CLK_TOP_MSDC30_0_SEL, 13),
|
|
GATE_PERI0(CLK_PERI_MSDC30_1, CLK_TOP_MSDC30_1_SEL, 14),
|
|
GATE_PERI0(CLK_PERI_MSDC30_2, CLK_TOP_MSDC30_2_SEL, 15),
|
|
GATE_PERI0(CLK_PERI_MSDC30_3, CLK_TOP_MSDC30_3_SEL, 16),
|
|
GATE_PERI0(CLK_PERI_MSDC50_3, CLK_TOP_EMMC_HCLK_SEL, 17),
|
|
GATE_PERI0(CLK_PERI_NLI, CLK_TOP_AXI_SEL, 18),
|
|
GATE_PERI0(CLK_PERI_UART0, CLK_TOP_AXI_SEL, 19),
|
|
GATE_PERI0(CLK_PERI_UART1, CLK_TOP_AXI_SEL, 20),
|
|
GATE_PERI0(CLK_PERI_UART2, CLK_TOP_AXI_SEL, 21),
|
|
GATE_PERI0(CLK_PERI_UART3, CLK_TOP_AXI_SEL, 22),
|
|
GATE_PERI0(CLK_PERI_BTIF, CLK_TOP_AXI_SEL, 23),
|
|
GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
|
|
GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
|
|
GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
|
|
GATE_PERI0_XTAL(CLK_PERI_I2C3, CLK_XTAL, 27),
|
|
GATE_PERI0_XTAL(CLK_PERI_AUXADC, CLK_XTAL, 28),
|
|
GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
|
|
GATE_PERI0_XTAL(CLK_PERI_ETH, CLK_XTAL, 30),
|
|
GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31),
|
|
|
|
GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0),
|
|
GATE_PERI1(CLK_PERI_USB_SLV, CLK_TOP_AXI_SEL, 1),
|
|
GATE_PERI1(CLK_PERI_GCPU, CLK_TOP_AXI_SEL, 2),
|
|
GATE_PERI1(CLK_PERI_NFI_ECC, CLK_TOP_NFI1X_PAD, 3),
|
|
GATE_PERI1(CLK_PERI_NFI_PAD, CLK_TOP_NFI1X_PAD, 4),
|
|
GATE_PERI1(CLK_PERI_FLASH, CLK_TOP_NFI2X_SEL, 5),
|
|
GATE_PERI1(CLK_PERI_HOST89_INT, CLK_TOP_AXI_SEL, 6),
|
|
GATE_PERI1(CLK_PERI_HOST89_SPI, CLK_TOP_SPI0_SEL, 7),
|
|
GATE_PERI1(CLK_PERI_HOST89_DVD, CLK_TOP_AUD2DVD_SEL, 8),
|
|
GATE_PERI1(CLK_PERI_SPI1, CLK_TOP_SPI1_SEL, 9),
|
|
GATE_PERI1(CLK_PERI_SPI2, CLK_TOP_SPI2_SEL, 10),
|
|
GATE_PERI1(CLK_PERI_FCI, CLK_TOP_MS_CARD_SEL, 11),
|
|
};
|
|
|
|
/* ethsys and hifsys */
|
|
static const struct mtk_gate_regs eth_hif_cg_regs = {
|
|
.sta_ofs = 0x30,
|
|
};
|
|
|
|
#define GATE_ETH_HIF(_id, _parent, _shift, _flag) { \
|
|
.id = _id, \
|
|
.parent = _parent, \
|
|
.regs = ð_hif_cg_regs, \
|
|
.shift = _shift, \
|
|
.flags = CLK_GATE_NO_SETCLR_INV | (_flag), \
|
|
}
|
|
|
|
#define GATE_ETH_HIF0(_id, _parent, _shift) \
|
|
GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_APMIXED)
|
|
|
|
#define GATE_ETH_HIF1(_id, _parent, _shift) \
|
|
GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
|
|
|
|
static const struct mtk_gate eth_cgs[] = {
|
|
GATE_ETH_HIF1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5),
|
|
GATE_ETH_HIF1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
|
|
GATE_ETH_HIF0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7),
|
|
GATE_ETH_HIF1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
|
|
GATE_ETH_HIF1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11),
|
|
GATE_ETH_HIF1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14),
|
|
GATE_ETH_HIF1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17),
|
|
GATE_ETH_HIF1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
|
|
};
|
|
|
|
static const struct mtk_gate hif_cgs[] = {
|
|
GATE_ETH_HIF1(CLK_HIFSYS_USB0PHY, CLK_TOP_ETHPLL_500M, 21),
|
|
GATE_ETH_HIF1(CLK_HIFSYS_USB1PHY, CLK_TOP_ETHPLL_500M, 22),
|
|
GATE_ETH_HIF1(CLK_HIFSYS_PCIE0, CLK_TOP_ETHPLL_500M, 24),
|
|
GATE_ETH_HIF1(CLK_HIFSYS_PCIE1, CLK_TOP_ETHPLL_500M, 25),
|
|
GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
|
|
};
|
|
|
|
static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = {
|
|
.xtal2_rate = 26 * MHZ,
|
|
.id_offs_map = pll_id_offs_map,
|
|
.plls = apmixed_plls,
|
|
};
|
|
|
|
static const struct mtk_clk_tree mt7623_topckgen_clk_tree = {
|
|
.xtal_rate = 26 * MHZ,
|
|
.id_offs_map = top_id_offs_map,
|
|
.fdivs_offs = top_id_offs_map[CLK_TOP_SYSPLL],
|
|
.muxes_offs = top_id_offs_map[CLK_TOP_AXI_SEL],
|
|
.fclks = top_fixed_clks,
|
|
.fdivs = top_fixed_divs,
|
|
.muxes = top_muxes,
|
|
};
|
|
|
|
static int mt7623_mcucfg_probe(struct udevice *dev)
|
|
{
|
|
void __iomem *base;
|
|
|
|
base = dev_read_addr_ptr(dev);
|
|
if (!base)
|
|
return -ENOENT;
|
|
|
|
clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
|
|
AXI_DIV_SEL(0x12));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt7623_apmixedsys_probe(struct udevice *dev)
|
|
{
|
|
struct mtk_clk_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
ret = mtk_common_clk_init(dev, &mt7623_apmixedsys_clk_tree);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* reduce clock square disable time */
|
|
writel(0x50001, priv->base + MT7623_CLKSQ_STB_CON0);
|
|
/* extend control timing to 1us */
|
|
writel(0x888, priv->base + MT7623_PLL_ISO_CON0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt7623_topckgen_probe(struct udevice *dev)
|
|
{
|
|
return mtk_common_clk_init(dev, &mt7623_topckgen_clk_tree);
|
|
}
|
|
|
|
static const struct mtk_clk_tree mt7623_clk_gate_tree = {
|
|
/* Each CLK ID for gates clock starts at index 1 */
|
|
.gates_offs = 1,
|
|
.xtal_rate = 26 * MHZ,
|
|
};
|
|
|
|
static int mt7623_infracfg_probe(struct udevice *dev)
|
|
{
|
|
return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
|
|
infra_cgs);
|
|
}
|
|
|
|
static const struct mtk_clk_tree mt7623_clk_peri_tree = {
|
|
.id_offs_map = peri_id_offs_map,
|
|
.muxes_offs = peri_id_offs_map[CLK_PERI_UART0_SEL],
|
|
.gates_offs = peri_id_offs_map[CLK_PERI_NFI],
|
|
.muxes = peri_muxes,
|
|
.gates = peri_cgs,
|
|
.xtal_rate = 26 * MHZ,
|
|
};
|
|
|
|
static int mt7623_pericfg_probe(struct udevice *dev)
|
|
{
|
|
return mtk_common_clk_infrasys_init(dev, &mt7623_clk_peri_tree);
|
|
}
|
|
|
|
static int mt7623_hifsys_probe(struct udevice *dev)
|
|
{
|
|
return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
|
|
hif_cgs);
|
|
}
|
|
|
|
static int mt7623_ethsys_probe(struct udevice *dev)
|
|
{
|
|
return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
|
|
eth_cgs);
|
|
}
|
|
|
|
static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
|
|
{
|
|
int ret = 0;
|
|
|
|
#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
|
|
ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
|
|
if (ret)
|
|
debug("Warning: failed to bind reset controller\n");
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct udevice_id mt7623_apmixed_compat[] = {
|
|
{ .compatible = "mediatek,mt7623-apmixedsys" },
|
|
{ }
|
|
};
|
|
|
|
static const struct udevice_id mt7623_topckgen_compat[] = {
|
|
{ .compatible = "mediatek,mt7623-topckgen" },
|
|
{ }
|
|
};
|
|
|
|
static const struct udevice_id mt7623_infracfg_compat[] = {
|
|
{ .compatible = "mediatek,mt7623-infracfg", },
|
|
{ }
|
|
};
|
|
|
|
static const struct udevice_id mt7623_pericfg_compat[] = {
|
|
{ .compatible = "mediatek,mt7623-pericfg", },
|
|
{ }
|
|
};
|
|
|
|
static const struct udevice_id mt7623_ethsys_compat[] = {
|
|
{ .compatible = "mediatek,mt7623-ethsys" },
|
|
{ }
|
|
};
|
|
|
|
static const struct udevice_id mt7623_hifsys_compat[] = {
|
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{ .compatible = "mediatek,mt7623-hifsys" },
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{ }
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};
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static const struct udevice_id mt7623_mcucfg_compat[] = {
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{ .compatible = "mediatek,mt7623-mcucfg" },
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{ }
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};
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U_BOOT_DRIVER(mtk_mcucfg) = {
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.name = "mt7623-mcucfg",
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.id = UCLASS_SYSCON,
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.of_match = mt7623_mcucfg_compat,
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.probe = mt7623_mcucfg_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
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.name = "mt7623-clock-apmixedsys",
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.id = UCLASS_CLK,
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.of_match = mt7623_apmixed_compat,
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.probe = mt7623_apmixedsys_probe,
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.priv_auto = sizeof(struct mtk_clk_priv),
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.ops = &mtk_clk_apmixedsys_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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U_BOOT_DRIVER(mtk_clk_topckgen) = {
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.name = "mt7623-clock-topckgen",
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.id = UCLASS_CLK,
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.of_match = mt7623_topckgen_compat,
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.probe = mt7623_topckgen_probe,
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.priv_auto = sizeof(struct mtk_clk_priv),
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.ops = &mtk_clk_topckgen_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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U_BOOT_DRIVER(mtk_clk_infracfg) = {
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.name = "mt7623-infracfg",
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.id = UCLASS_CLK,
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.of_match = mt7623_infracfg_compat,
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.probe = mt7623_infracfg_probe,
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.priv_auto = sizeof(struct mtk_cg_priv),
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.ops = &mtk_clk_gate_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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U_BOOT_DRIVER(mtk_clk_pericfg) = {
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.name = "mt7623-pericfg",
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.id = UCLASS_CLK,
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.of_match = mt7623_pericfg_compat,
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.probe = mt7623_pericfg_probe,
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.priv_auto = sizeof(struct mtk_cg_priv),
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.ops = &mtk_clk_infrasys_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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U_BOOT_DRIVER(mtk_clk_hifsys) = {
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.name = "mt7623-clock-hifsys",
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.id = UCLASS_CLK,
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.of_match = mt7623_hifsys_compat,
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.probe = mt7623_hifsys_probe,
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.bind = mt7623_ethsys_hifsys_bind,
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.priv_auto = sizeof(struct mtk_cg_priv),
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.ops = &mtk_clk_gate_ops,
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};
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U_BOOT_DRIVER(mtk_clk_ethsys) = {
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.name = "mt7623-clock-ethsys",
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.id = UCLASS_CLK,
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.of_match = mt7623_ethsys_compat,
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.probe = mt7623_ethsys_probe,
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.bind = mt7623_ethsys_hifsys_bind,
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.priv_auto = sizeof(struct mtk_cg_priv),
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.ops = &mtk_clk_gate_ops,
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};
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