304 lines
7.2 KiB
C
304 lines
7.2 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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/*
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* Copyright (C) 2014-2018 Amlogic, Inc. All rights reserved.
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*
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* All information contained herein is Amlogic confidential.
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*
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* This software is provided to you pursuant to Software License Agreement
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* (SLA) with Amlogic Inc ("Amlogic"). This software may be used
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* only in accordance with the terms of this agreement.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification is strictly prohibited without prior written permission from
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* Amlogic.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <mmu.h>
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#include <cache_v8.h>
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#include <serial.h>
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#include <io.h>
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#include "ram_compress.h"
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#include "platform_def.h"
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#include "regs.h"
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/* Asm functions from cache_v7_asm.S */
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void v7_flush_dcache_all(void);
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void v7_invalidate_dcache_all(void);
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u32 bl2e_ttbr0 = 0, bl2e_dacr = 0, bl2e_sctlr = 0;
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//porting from arch/arm/lib/cache-cp15.c
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static inline unsigned int get_cr(void)
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{
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unsigned int val;
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asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
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:
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: "cc");
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return val;
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}
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static inline void set_cr(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
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: "r" (val)
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: "cc");
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asm volatile("isb");
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}
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u32 __asm_get_sctlr(void)
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{
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return get_cr();
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}
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void __asm_set_sctlr(u32 val)
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{
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set_cr(val);
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}
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//porting from arch/arm/cpu/armv7/cache_v7.c
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/* Invalidate entire I-cache and branch predictor array */
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void invalidate_icache_all(void)
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{
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/*
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* Invalidate all instruction caches to PoU.
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* Also flushes branch target cache.
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*/
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asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
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/* Invalidate entire branch predictor array */
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asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
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/* Full system DSB - make sure that the invalidation is complete */
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asm volatile("dsb");
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/* ISB - make sure the instruction stream sees it */
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asm volatile("isb");
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}
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/* Invalidate TLB */
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static void invalidate_tlb_all(void)
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{
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/* Invalidate entire unified TLB */
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asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
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/* Invalidate entire data TLB */
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asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
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/* Invalidate entire instruction TLB */
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asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
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/* Full system DSB - make sure that the invalidation is complete */
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asm volatile("dsb");
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/* Full system ISB - make sure the instruction stream sees it */
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asm volatile("isb");
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}
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void get_bl2e_mmu_state(void)
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{
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bl2e_ttbr0 = __asm_get_ttbr0();
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bl2e_dacr = __asm_get_dacr();
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bl2e_sctlr = get_cr();
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serial_puts("Get bl2e mmu table. ttbr0_EL2:0x");
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serial_put_hex(bl2e_ttbr0, 32);
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serial_puts(", dacr_EL2:0x");
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serial_put_hex(bl2e_dacr, 32);
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serial_puts(", sctlr_EL2:0x");
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serial_put_hex(bl2e_sctlr, 32);
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serial_puts("\n");
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}
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void set_bl2e_mmu_state(void)
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{
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__asm_set_ttbr0(bl2e_ttbr0);
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__asm_set_dacr(bl2e_dacr);
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set_cr(bl2e_sctlr);
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serial_puts("Overwrite bl2e mmu table for bl33 board_f.");
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}
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void set_pgtable_section(u32 *pgtable, u32 index, u32 phys, u32 flags)
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{
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u32 desc;
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desc = (phys & 0xFFF00000) // section base
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| (2 << 0) // bit[1:0] = 10 → section
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| (1 << 10) // AP[2] (full access)
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| (3 << 10); // AP[1:0] = 11 (RW)
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desc |= flags; // TEX/C/B 等
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pgtable[index] = desc;
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}
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/*
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* Section Mapping (1MB) + Identity Mapping
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* VA == PA, using ARMv7 first-level section descriptors.
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*
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* Each entry maps one 1MB region:
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* section[i] -> physical base (i << 20)
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*
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* 4GB is initially mapped as Device memory,
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* then DDR is overwritten as Normal cacheable memory.
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*/
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void mmu_setup(unsigned long ddr_size)
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{
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u32 *page_table = (u32 *)CONFIG_AML_MMU_ADDR;
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u32 i, reg;
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unsigned long nTotal;
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/* 1. clean pagetable */
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for (i = 0; i < PAGE_ENTRIES; i++) {
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page_table[i] = 0;
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}
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/* 2. aarch32 full ddr is 4GB: DEVICE ( avoid MMIO crash) */
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for (i = 0; i < PAGE_ENTRIES; i++) {
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page_table[i] =
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(i << SECTION_SHIFT) |
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PMD_TYPE_SECT |
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PMD_SECT_AF |
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MT_DEVICE;
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}
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/* 3. DDR 0~512MB change to NORMAL memory */
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nTotal = readl(REG_MDUMP_CPUBOOT_STATUS) & (AMLOGIC_USERAM_MASK & ~RAMDUMP_STICKY_DMA_MASK);
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nTotal = ((nTotal - 1) / 64 + 1) * 64; /* ddr size must big than 64MB */
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nTotal = nTotal ? nTotal : (ddr_size >> 20);
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serial_puts("mmu: DDR size is ");
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serial_put_dec(nTotal);
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serial_puts("MB\n");
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for (i = 0; i < (nTotal / SECTION_SIZE_MB); i++) {
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page_table[i] =
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(i << SECTION_SHIFT) |
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PMD_TYPE_SECT |
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PMD_SECT_AF |
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MT_NORMAL;
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}
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/* 4. TTBCR = 0 (disable LPAE / full TTBR0 space) */
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asm volatile("mcr p15, 0, %0, c2, c0, 2"
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: : "r"(0) : "memory");
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/* 5. TTBR0 */
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reg = (u32)page_table;
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/* cache policy（WB/WA） */
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reg &= TTBR0_BASE_ADDR_MASK;
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reg |= TTBR0_RGN_WB;
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reg |= TTBR0_IRGN_WB;
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asm volatile("mcr p15, 0, %0, c2, c0, 0"
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: : "r"(reg) : "memory");
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/* 6. DACR = all domains client */
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asm volatile("mcr p15, 0, %0, c3, c0, 0"
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: : "r"(0x55555555));
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asm volatile("dsb");
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asm volatile("isb");
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/* 7. ENABLE MMU */
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reg = get_cr();
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reg |= (1 << 0); // M bit
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asm volatile("mcr p15, 0, %0, c1, c0, 0"
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: : "r"(reg) : "memory");
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asm volatile("dsb");
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asm volatile("isb");
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serial_puts("mmu: enabled OK\n");
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}
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void enable_dcache(unsigned long ddr_size)
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{
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uint32_t reg;
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/* already enabled */
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if (get_cr() & CR_C)
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return;
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/*
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* D-cache requires MMU enabled first.
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* Build 1MB section identity mapping if MMU is still off.
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*/
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if (!(get_cr() & CR_M)) {
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/*
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* Optional but recommended:
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* invalidate TLB before installing new translation base
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*/
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invalidate_tlb_all();
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/*
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* Setup TTBR0 / DACR / enable CR_M
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*/
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mmu_setup(ddr_size);
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}
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reg = get_cr();
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reg |= CR_C;
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set_cr(reg);
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}
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void enable_icache(void)
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{
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uint32_t reg;
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invalidate_icache_all();
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reg = get_cr();
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set_cr(reg | CR_I);
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}
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void disable_dcache(void)
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{
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uint32_t reg;
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reg = get_cr();
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if (!(reg & CR_C))
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return;
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set_cr(reg & ~(CR_C | CR_M));
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v7_flush_dcache_all();
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invalidate_tlb_all();
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}
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void disable_icache(void)
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{
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uint32_t reg;
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/* 1. Invalidate I-cache first */
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invalidate_icache_all();
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/* 2. Disable I-cache */
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reg = get_cr();
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reg &= ~CR_I;
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set_cr(reg);
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/* 3. Ensure new state takes effect */
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asm volatile("isb");
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}
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// C4_aarch32 porting from uboot/v2025/arch/arm/lib/cache-cp15.c
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void enable_caches(unsigned long ddr_size)
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{
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enable_icache();
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enable_dcache(ddr_size);
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}
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void disable_caches(void)
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{
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disable_icache();
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disable_dcache();
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}
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