114 lines
3.9 KiB
C
114 lines
3.9 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _ASM_ARMV8_MMU_H_
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#define _ASM_ARMV8_MMU_H_
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/***************************************************************
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* AArch32 (ARMv7-A) MMU / Page Table Definitions
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*
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* Description:
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* - Uses 1MB section mapping
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* - Typical usage: U-Boot / BL33 identity mapping
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* - Applicable to Cortex-A7 / Cortex-A9 / Cortex-A53 (AArch32 mode)
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***************************************************************/
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#define BIT(nr) (1 << nr)
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typedef unsigned int u32;
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#ifdef __ASSEMBLY__
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#define _AC(X, Y) X
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#else
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#define _AC(X, Y) (X##Y)
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#endif
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#define UL(x) _AC(x, UL)
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/* ============================================================
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* Page Table
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* ============================================================ */
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/* 4GB address space / 1MB section = 4096 entries */
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#define PAGE_ENTRIES (0x100000000ULL >> SECTION_SHIFT)
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/* page table size (16KB or 64KB aligned depending platform) */
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#define PGTABLE_SIZE (0x10000)
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/* ============================================================
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* Section mapping (1MB granularity)
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* ============================================================ */
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#define SECTION_SHIFT 20
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#define SECTION_SIZE (1UL << SECTION_SHIFT)
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#define SECTION_SIZE_MB (SECTION_SIZE >> 20)
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/* ============================================================
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* Section descriptor format (ARMv7-A)
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* ============================================================
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* [1:0] = descriptor type (10 = section)
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* [10] = APX / AF (access flag)
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* [31:20] = physical base address
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* ============================================================ */
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#define PMD_TYPE_SECT (0x2)
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#define PMD_SECT_AF BIT(10)
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/* ============================================================
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* Memory Attribute (TEX / C / B)
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* ============================================================
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* ARMv7-A section attributes:
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*
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* TEX C B meaning
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* 000 1 1 Write-back, write-allocate (Normal memory)
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* 000 0 0 Strongly ordered / Device
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* ============================================================ */
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/* Device memory (non-cacheable) */
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#define MT_DEVICE (0 << 12 | 0 << 3 | 0 << 2)
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/* Normal cacheable memory (WBWA) */
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#define MT_NORMAL (0 << 12 | 1 << 3 | 1 << 2)
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/* ============================================================
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* TTBR0 configuration (ARMv7-A)
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* ============================================================
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* TTBR0 bits:
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* - Base address [31:14]
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* - IRGN / RGN cache policy
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* ============================================================ */
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#define TTBR0_BASE_ADDR_MASK 0xFFFFC000
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/* Outer cache policy */
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#define TTBR0_RGN_NC (0 << 3)
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#define TTBR0_RGN_WBWA (1 << 3)
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#define TTBR0_RGN_WT (2 << 3)
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#define TTBR0_RGN_WB (3 << 3)
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/* Inner cache policy (IRGN[1:0] + TTBR0[6]) */
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#define TTBR0_IRGN_NC ((0 << 0) | (0 << 6))
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#define TTBR0_IRGN_WBWA ((0 << 0) | (1 << 6))
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#define TTBR0_IRGN_WT ((1 << 0) | (0 << 6))
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#define TTBR0_IRGN_WB ((1 << 0) | (1 << 6))
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/* ============================================================
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* Cache policy (legacy U-Boot style)
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* ============================================================ */
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enum dcache_option {
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DCACHE_OFF = (0 << 2),
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DCACHE_WRITETHROUGH = (3 << 2),
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DCACHE_WRITEBACK = (4 << 2),
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DCACHE_WRITEALLOC = (4 << 2),
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};
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#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
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/* ============================================================
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* SCTLR (CP15 System Control Register)
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* ============================================================ */
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#define CR_M BIT(0) /* MMU enable */
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#define CR_A BIT(1) /* Alignment check */
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#define CR_C BIT(2) /* Data cache enable */
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#define CR_W BIT(3) /* Write buffer enable */
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#define CR_Z BIT(11) /* Branch prediction enable */
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#define CR_I BIT(12) /* Instruction cache enable */
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#define CR_V BIT(13) /* Vector base high/low */
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#define CR_EE BIT(25) /* Endianness (0=little,1=big) */
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#endif /* _ASM_ARMV8_MMU_H_ */
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