32 lines
795 B
C
32 lines
795 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <[email protected]>
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*/
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#ifndef __ASM_RISCV_SYSTEM_H
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#define __ASM_RISCV_SYSTEM_H
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#include <asm/csr.h>
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struct event;
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/*
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* Interupt configuration macros
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*/
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#define local_irq_save(__flags) \
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do { \
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__flags = csr_read_clear(CSR_SSTATUS, SR_SIE) & SR_SIE; \
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} while (0)
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#define local_irq_restore(__flags) \
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do { \
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csr_set(CSR_SSTATUS, __flags & SR_SIE); \
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} while (0)
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/* Hook to set up the CPU (called from SPL too) */
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int riscv_cpu_setup(void);
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#endif /* __ASM_RISCV_SYSTEM_H */
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