65 lines
1.3 KiB
ArmAsm
65 lines
1.3 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2014-2015 Freescale Semiconductor
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*
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* Extracted from armv8/start.S
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/gic.h>
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#include <asm/macro.h>
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.align 2
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ENTRY(secondary_boot_func)
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/*
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* MPIDR_EL1 Fields:
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* MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
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* MPIDR[7:2] = AFF0_RES
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* MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
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* MPIDR[23:16] = AFF2_CLUSTERID
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* MPIDR[24] = MT
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* MPIDR[29:25] = RES0
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* MPIDR[30] = U
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* MPIDR[31] = ME
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* MPIDR[39:32] = AFF3
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*
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* Linear Processor ID (LPID) calculation from MPIDR_EL1:
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* (We only use AFF0_CPUID and AFF1_CLUSTERID for now
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* until AFF2_CLUSTERID and AFF3 have non-zero values)
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*
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* LPID = MPIDR[15:8] | MPIDR[1:0]
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*/
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mrs x0, mpidr_el1
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and x1, x0, #1<<24
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cmp x1, #0
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beq 1f
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lsr x0, x0, #8
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1:
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ubfx x1, x0, #8, #8
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ubfx x0, x0, #0, #8
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lsl x1, x1, 2 /* cluster0 has 4 cores*/
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add x0, x0, x1
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mov x2, x0
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bl secondary_bootup_f
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mov x0, x2
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bl get_smp_sp
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bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
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mrs x0, CurrentEL
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cmp x0, #CurrentEL_EL2
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b.ne 2f
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ldr x0, =(HCR_EL2_RW_AARCH64 | HCR_TGE)
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mrs x1, hcr_el2
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orr x1, x1, x0
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msr hcr_el2, x1
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2:
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bl secondary_start
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ENDPROC(secondary_boot_func)
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.align 3
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.globl CPU_RELEASE_ADDR
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CPU_RELEASE_ADDR:
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.quad secondary_boot_func
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