166 lines
3.7 KiB
C
166 lines
3.7 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/io.h>
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#include <asm/arch/secure_apb.h>
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#include <asm/arch/romboot.h>
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#include <asm/arch/cpu_reset.h>
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#include <amlogic/cpu_id.h>
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int do_ddr2pll(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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char *endp;
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unsigned long pll, zqcr;
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/* need at least two arguments */
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if (argc < 2)
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goto usage;
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pll = simple_strtoul(argv[1], &endp,0);
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if (*argv[1] == 0 || *endp != 0) {
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printf ("Error: Wrong format parament!\n");
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return 1;
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}
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if (argc >2)
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{
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zqcr = simple_strtoul(argv[2], &endp, 16);
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if (*argv[2] == 0 || *endp != 0) {
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zqcr = 0;
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}
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}
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else
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{
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zqcr = 0;
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}
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#if defined(CONFIG_M6TV) || defined(CONFIG_M6TVD)
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writel(zqcr | (0x3c << 24), P_PREG_STICKY_REG0);
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#else
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writel(zqcr | (0xf13 << 20), P_PREG_STICKY_REG0);
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#endif
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writel(pll | (readl(P_PREG_STICKY_REG1)), P_PREG_STICKY_REG1);
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printf("Set pll done [0x%08x]\n", readl(P_PREG_STICKY_REG1));
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#ifdef CONFIG_M8B
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writel(0xf080000 | 2000, WATCHDOG_TC);
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#else
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reset_system();
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#endif
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return 0;
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usage:
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cmd_usage(cmdtp);
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return 1;
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}
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U_BOOT_CMD(
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d2pll, 5, 1, do_ddr2pll,
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"DDR set PLL function",
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"DDR PLL set: d2pll PLL [ZQCR], e...g... 0x1022c.\n"
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);
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#define DDR_FULL_TEST_CTRL_BIT 21 //use sticky1 bit21
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int do_ddrft(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
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unsigned long ddr_full_test = 0;
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//printf("sticky1: 0x%x\n", readl(P_PREG_STICKY_REG1));
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if (get_cpu_id().family_id <= MESON_CPU_MAJOR_ID_GXTVBB) {
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printf("Only support gxl/gxm/txl... chips!\n");
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return 0;
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}
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if (argc == 1) {
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/* no parameters, switch 1/0 */
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if ((readl(P_PREG_STICKY_REG1)) & (1<<DDR_FULL_TEST_CTRL_BIT)) {
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writel((~(1<<DDR_FULL_TEST_CTRL_BIT)) & (readl(P_PREG_STICKY_REG1)), P_PREG_STICKY_REG1);
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}
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else {
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writel((1<<DDR_FULL_TEST_CTRL_BIT) | (readl(P_PREG_STICKY_REG1)), P_PREG_STICKY_REG1);
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}
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}
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else if (argc == 2) {
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ddr_full_test = simple_strtoul(argv[1], NULL,0);
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if (ddr_full_test)
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ddr_full_test = 1;
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writel((~(1<<DDR_FULL_TEST_CTRL_BIT)) & (readl(P_PREG_STICKY_REG1)), P_PREG_STICKY_REG1);
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writel((ddr_full_test << DDR_FULL_TEST_CTRL_BIT) | (readl(P_PREG_STICKY_REG1)), P_PREG_STICKY_REG1);
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}
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//printf("sticky1: 0x%x\n", readl(P_PREG_STICKY_REG1));
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if (readl(P_PREG_STICKY_REG1) & (1<<DDR_FULL_TEST_CTRL_BIT))
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printf("ddr full test enabled!\n");
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else
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printf("ddr full test disabled!\n");
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return 0;
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}
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/* ddr full test support, co-work with d2pll function */
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/*
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before d2pll command, use
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ddrft 1
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cmd enable ddr full test function
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*/
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U_BOOT_CMD(
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ddrft, 5, 1, do_ddrft,
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"Enable/Disable ddr full test at runtime\n\nOnly support gxl/gxm/txl",
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"[1/0]\n"
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);
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int do_ddr_sram_tune(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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char *endp;
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unsigned long pll, zqcr;
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/* need at least two arguments */
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if (argc < 2)
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goto usage;
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pll = simple_strtoul(argv[1], &endp, 16);
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if (*argv[1] == 0 || *endp != 0) {
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printf ("Error: Wrong format parament!\n");
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return 1;
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}
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if (argc >2)
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{
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zqcr = simple_strtoul(argv[2], &endp, 16);
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if (*argv[2] == 0 || *endp != 0) {
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zqcr = 0;
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}
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}
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else
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{
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zqcr = 0;
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}
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#if defined(CONFIG_M6TV) || defined(CONFIG_M6TVD)
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writel(zqcr | (0x3c << 24), P_PREG_STICKY_REG0);
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#else
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writel(zqcr | (0xf13 << 20), P_PREG_STICKY_REG0);
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#endif
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//writel(P_PREG_STICKY_REG1, pll);
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writel(pll|(1<<31), P_PREG_STICKY_REG1);//modify
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printf("Set pll done [0x%08x]\n", readl(P_PREG_STICKY_REG1));
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#ifdef CONFIG_M8B
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writel(0xf080000 | 2000, WATCHDOG_TC);
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#else
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reset_system();
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#endif
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return 0;
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usage:
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cmd_usage(cmdtp);
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return 1;
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}
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U_BOOT_CMD(
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ddr_sram_tune, 5, 1, do_ddr_sram_tune,
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"DDR sram tune dqs",
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"ddr_sram_tune PLL [ZQCR], e...g... 0x1022c.\n\n"
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);
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