374 lines
11 KiB
C
374 lines
11 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __CRG_UDC_H__
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#define __CRG_UDC_H__
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#define CRG_UCCR_OFFSET 0x2400
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#define CRG_UICR_OFFSET 0x2500
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#define CRG_UICR_STRIDE 0x20
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/* corigine usb 3.0 device core register macros */
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struct crg_uccr {
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u32 capability; /*0x00*/
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u32 resv0[3];
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u32 config0; /*0x10*/
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u32 config1;
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u32 resv1[2];
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u32 control; /*0x20*/
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u32 status;
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u32 dcbaplo;
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u32 dcbaphi;
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u32 portsc;
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u32 u3portpmsc;
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u32 u2portpmsc;
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u32 u3portli;
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u32 doorbell; /*0x40*/
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u32 mfindex;
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u32 speed_select;
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u32 resv3[5];
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u32 ep_enable; /*0x60*/
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u32 ep_running;
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u32 resv4[2];
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u32 cmd_param0; /*0x70*/
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u32 cmd_param1;
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u32 cmd_control;
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u32 resv5[1];
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u32 odb_capability; /*0x80*/
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u32 resv6[3];
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u32 odb_config[8];
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u32 debug0; /*0xB0*/
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};
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struct crg_uicr {
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u32 iman;
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u32 imod;
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u32 erstsz;
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u32 resv0;
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u32 erstbalo; /*0x10*/
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u32 erstbahi;
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u32 erdplo;
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u32 erdphi;
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};
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#define SETF_VAR(field, var, fieldval) \
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(var = (((var) & ~(field ## _MASK)) | \
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(((fieldval) << field ## _SHIFT) & (field ## _MASK))))
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#define GETF(field, val) \
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(((val) & (field ## _MASK)) >> (field ## _SHIFT))
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#define MAKEF_VAR(field, fieldval) \
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(((fieldval) << field ## _SHIFT) & (field ## _MASK))
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/* interrupt registers array */
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#define CRG_U3DC_IRS_BASE (0x100L)
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#define CRG_U3DC_IRS_IMAN(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x00L)
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#define CRG_U3DC_IRS_IMOD(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x04L)
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#define CRG_U3DC_IRS_ERSTSZ(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x08L)
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#define CRG_U3DC_IRS_ERSTBALO(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x10L)
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#define CRG_U3DC_IRS_ERSTBAHI(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x14L)
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#define CRG_U3DC_IRS_ERDPLO(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x18L)
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#define CRG_U3DC_IRS_ERDPHI(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x20L)
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/* reg config 0 & 1*/
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#define CRG_U3DC_CFG0_MAXSPEED_MASK (0xfL<<0)
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#define CRG_U3DC_CFG0_MAXSPEED_FS (0x1L<<0)
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#define CRG_U3DC_CFG0_MAXSPEED_HS (0x3L<<0)
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#define CRG_U3DC_CFG0_MAXSPEED_SS (0x4L<<0)
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#define CRG_U3DC_CFG0_MAXSPEED_SSP (0x5L<<0)
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#define CRG_U3DC_CFG1_CSC_EVENT_EN (0x1L<<0)
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#define CRG_U3DC_CFG1_PEC_EVENT_EN (0x1L<<1)
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#define CRG_U3DC_CFG1_PPC_EVENT_EN (0x1L<<3)
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#define CRG_U3DC_CFG1_PRC_EVENT_EN (0x1L<<4)
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#define CRG_U3DC_CFG1_PLC_EVENT_EN (0x1L<<5)
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#define CRG_U3DC_CFG1_CEC_EVENT_EN (0x1L<<6)
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#define CRG_U3DC_CFG1_U3_ENTRY_EN (0x1L<<8)
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#define CRG_U3DC_CFG1_L1_ENTRY_EN (0x1L<<9)
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#define CRG_U3DC_CFG1_U3_RESUME_EN (0x1L<<10)
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#define CRG_U3DC_CFG1_L1_RESUME_EN (0x1L<<11)
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#define CRG_U3DC_CFG1_INACTIVE_PLC_EN (0x1L<<12)
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#define CRG_U3DC_CFG1_U3_RESUME_NORESP_PLC_EN (0x1L<<13)
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#define CRG_U3DC_CFG1_U2_RESUME_NORESP_PLC_EN (0x1L<<14)
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#define CRG_U3DC_CFG1_SETUP_EVENT_EN (0x1L<<16)
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/* ctrl register*/
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#define CRG_U3DC_CTRL_RUN (1L<<0)
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#define CRG_U3DC_CTRL_STOP (0L<<0)
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#define CRG_U3DC_CTRL_SWRST (1L<<1)
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#define CRG_U3DC_CTRL_INT_EN (1L<<2)
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#define CRG_U3DC_CTRL_SYSERR_EN (1L<<3)/*only AXI bus error*/
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#define CRG_U3DC_CTRL_EWE (1L<<10)
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#define CRG_U3DC_CTRL_KP_CNCT (1L<<11)
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/*status register*/
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#define CRG_U3DC_STATUS_DEV_CTRL_HALT (1L << 0)
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#define CRG_U3DC_STATUS_SYS_ERR (1L << 2)
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#define CRG_U3DC_STATUS_EINT (1L << 3)
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/*portsc register*/
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#define CRG_U3DC_PORTSC_CCS (1L << 0)
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#define CRG_U3DC_PORTSC_PED (1L << 1)
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#define CRG_U3DC_PORTSC_PP (1L << 3)
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#define CRG_U3DC_PORTSC_PR (1L << 4)
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#define CRG_U3DC_PORTSC_PLS_SHIFT (5)
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#define CRG_U3DC_PORTSC_PLS_MASK (0xf << CRG_U3DC_PORTSC_PLS_SHIFT)
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#define CRG_U3DC_PORTSC_PLS(fv) (MAKEF_VAR(CRG_U3DC_PORTSC_PLS, (fv)))
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#define CRG_U3DC_PORTSC_PLS_GET(v) (GETF(CRG_U3DC_PORTSC_PLS, (v)))
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#define CRG_U3DC_PORTSC_SPEED_SHIFT (10)
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#define CRG_U3DC_PORTSC_SPEED_MASK \
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(0xf << CRG_U3DC_PORTSC_SPEED_SHIFT)
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#define CRG_U3DC_PORTSC_SPEED(fv) \
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(MAKEF_VAR(CRG_U3DC_PORTSC_SPEED, (fv)))
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#define CRG_U3DC_PORTSC_SPEED_GET(v) \
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(GETF(CRG_U3DC_PORTSC_SPEED, (v)))
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#define CRG_U3DC_PORTSC_SPEED_FS (0x1)
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#define CRG_U3DC_PORTSC_SPEED_LS (0x2)
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#define CRG_U3DC_PORTSC_SPEED_HS (0x3)
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#define CRG_U3DC_PORTSC_SPEED_SS (0x4)
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#define CRG_U3DC_PORTSC_SPEED_SSP (0x5)
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#define CRG_U3DC_PORTSC_LWS (1L << 16)
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#define CRG_U3DC_PORTSC_CSC (1L << 17)
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#define CRG_U3DC_PORTSC_PEC (1L << 18)
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#define CRG_U3DC_PORTSC_PPC (1L << 20)
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#define CRG_U3DC_PORTSC_PRC (1L << 21)
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#define CRG_U3DC_PORTSC_PLC (1L << 22)
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#define CRG_U3DC_PORTSC_CEC (1L << 23)
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#define CRG_U3DC_PORTSC_WCE (1L << 25)
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#define CRG_U3DC_PORTSC_WDE (1L << 26)
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#define CRG_U3DC_PORTSC_WPR (1L << 31)
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#define PORTSC_W1C_MASK (CRG_U3DC_PORTSC_CSC | \
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CRG_U3DC_PORTSC_PEC | \
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CRG_U3DC_PORTSC_PPC | \
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CRG_U3DC_PORTSC_PRC | \
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CRG_U3DC_PORTSC_PLC | \
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CRG_U3DC_PORTSC_CEC)
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#define PORTSC_WRITE_MASK (~PORTSC_W1C_MASK)
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/* u3portpmsc */
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#define CRG_U3DC_U3PORTPM_U1TMOUT_SHIFT (0)
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#define CRG_U3DC_U3PORTPM_U1TMOUT_MASK \
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(0xff << CRG_U3DC_U3PORTPM_U1TMOUT_SHIFT)
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#define CRG_U3DC_U3PORTPM_U1TMOUT(fv) \
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(MAKEF_VAR(CRG_U3DC_U3PORTPM_U1TMOUT, (fv)))
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#define CRG_U3DC_U3PORTPM_U2TMOUT_SHIFT (8)
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#define CRG_U3DC_U3PORTPM_U2TMOUT_MASK \
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(0xff << CRG_U3DC_U3PORTPM_U2TMOUT_SHIFT)
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#define CRG_U3DC_U3PORTPM_U2TMOUT(fv) \
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(MAKEF_VAR(CRG_U3DC_U3PORTPM_U2TMOUT, (fv)))
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#define CRG_U3DC_U3PORTPM_FLA (1L << 16)
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#define CRG_U3DC_U3PORTPM_U1IEN_SHIFT (20)
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#define CRG_U3DC_U3PORTPM_U1IEN \
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(1L << CRG_U3DC_U3PORTPM_U1IEN_SHIFT)
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#define CRG_U3DC_U3PORTPM_U2IEN_SHIFT (21)
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#define CRG_U3DC_U3PORTPM_U2IEN \
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(1L << CRG_U3DC_U3PORTPM_U2IEN_SHIFT)
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#define CRG_U3DC_U3PORTPM_U1AEN_SHIFT (22)
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#define CRG_U3DC_U3PORTPM_U1AEN \
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(1L << CRG_U3DC_U3PORTPM_U1AEN_SHIFT)
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#define CRG_U3DC_U3PORTPM_U2AEN_SHIFT (23)
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#define CRG_U3DC_U3PORTPM_U2AEN \
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(1L << CRG_U3DC_U3PORTPM_U2AEN_SHIFT)
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#define CRG_U3DC_U3PORTPM_U1U2TMOUT_SHIFT (24)
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#define CRG_U3DC_U3PORTPM_U1U2TMOUT_MASK \
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(0xff << CRG_U3DC_U3PORTPM_U1U2TMOUT_SHIFT)
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/* u2portpmsc */
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#define CRG_U3DC_U2PORTPM_RJ_TH_SHIFT (0)
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#define CRG_U3DC_U2PORTPM_RJ_TH_MASK \
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(0xf << CRG_U3DC_U2PORTPM_RJ_TH_SHIFT)
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#define CRG_U3DC_U2PORTPM_RJ_TH(fv) \
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(MAKEF_VAR(CRG_U3DC_U2PORTPM_RJ_TH, (fv)))
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#define CRG_U3DC_U2PORTPM_DS_TH_SHIFT (4)
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#define CRG_U3DC_U2PORTPM_DS_TH_MASK \
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(0xf << CRG_U3DC_U2PORTPM_DS_TH_SHIFT)
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#define CRG_U3DC_U2PORTPM_DS_TH(fv) \
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(MAKEF_VAR(CRG_U3DC_U2PORTPM_DS_TH, (fv)))
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#define CRG_U3DC_U2PORTPM_LPM_EN (0x1 << 8)
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#define CRG_U3DC_U2PORTPM_RJ_TH_EN (0x1 << 9)
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#define CRG_U3DC_U2PORTPM_DS_EN (0x1 << 10)
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#define CRG_U3DC_U2PORTPM_SLP_EN (0x1 << 11)
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#define CRG_U3DC_U2PORTPM_LPM_FACK (0x1 << 12)
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#define CRG_U3DC_U2PORTPM_L1_AEX (0x1 << 13)
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#define CRG_U3DC_U2PORTPM_H_B_SHIFT (16)
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#define CRG_U3DC_U2PORTPM_H_B_MASK \
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(0xf << CRG_U3DC_U2PORTPM_H_B_SHIFT)
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#define CRG_U3DC_U2PORTPM_H_B(fv) \
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(MAKEF_VAR(CRG_U3DC_U2PORTPM_H_B, (fv)))
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#define CRG_U3DC_U2PORTPM_RWE (0x1 << 20)
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#define CRG_U3DC_U2PORTPM_TM_SHIFT (28)
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#define CRG_U3DC_U2PORTPM_TM_MASK \
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(0xf << CRG_U3DC_U2PORTPM_TM_SHIFT)
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#define CRG_U3DC_U2PORTPM_TM(fv) \
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(MAKEF_VAR(CRG_U3DC_U2PORTPM_TM, (fv)))
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/* doorbell register*/
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#define CRG_U3DC_DB_TARGET_SHIFT (0)
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#define CRG_U3DC_DB_TARGET_MASK \
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(0x1f << CRG_U3DC_DB_TARGET_SHIFT)
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#define CRG_U3DC_DB_TARGET(fv) \
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(MAKEF_VAR(CRG_U3DC_DB_TARGET, (fv)))
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/* odb registers*/
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#define CRG_U3DC_ODBCFG_2N_OFFSET_SHIFT (0)
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#define CRG_U3DC_ODBCFG_2N_OFFSET_MASK \
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(0x3ff << CRG_U3DC_ODBCFG_2N_OFFSET_SHIFT)
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#define CRG_U3DC_ODBCFG_2N_OFFSET(fv) \
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(MAKEF_VAR(CRG_U3DC_ODBCFG_2N_OFFSET, (fv)))
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#define CRG_U3DC_ODBCFG_2N_SIZE_SHIFT (10)
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#define CRG_U3DC_ODBCFG_2N_SIZE_MASK \
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(0x7 << CRG_U3DC_ODBCFG_2N_SIZE_SHIFT)
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#define CRG_U3DC_ODBCFG_2N_SIZE(fv) \
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(MAKEF_VAR(CRG_U3DC_ODBCFG_2N_SIZE, (fv)))
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#define CRG_U3DC_ODBCFG_2N1_OFFSET_SHIFT (16)
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#define CRG_U3DC_ODBCFG_2N1_OFFSET_MASK \
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(0x3ff << CRG_U3DC_ODBCFG_2N1_OFFSET_SHIFT)
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#define CRG_U3DC_ODBCFG_2N1_OFFSET(fv) \
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(MAKEF_VAR(CRG_U3DC_ODBCFG_2N1_OFFSET, (fv)))
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#define CRG_U3DC_ODBCFG_2N1_SIZE_SHIFT (26)
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#define CRG_U3DC_ODBCFG_2N1_SIZE_MASK \
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(0x7 << CRG_U3DC_ODBCFG_2N1_SIZE_SHIFT)
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#define CRG_U3DC_ODBCFG_2N1_SIZE(fv) \
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(MAKEF_VAR(CRG_U3DC_ODBCFG_2N1_SIZE, (fv)))
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/* command control register*/
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#define CRG_U3DC_CMD_CTRL_ACTIVE_SHIFT (0)
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#define CRG_U3DC_CMD_CTRL_ACTIVE \
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(1L<<CRG_U3DC_CMD_CTRL_ACTIVE_SHIFT)
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#define CRG_U3DC_CMD_CTRL_IOC_SHIFT (1)
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#define CRG_U3DC_CMD_CTRL_IOC_EN \
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(1L<<CRG_U3DC_CMD_CTRL_IOC_SHIFT)
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#define CRG_U3DC_CMD_CTRL_TYPE_SHIFT (4)
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#define CRG_U3DC_CMD_CTRL_TYPE_MASK \
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(0xf<<CRG_U3DC_CMD_CTRL_TYPE_SHIFT)
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#define CRG_U3DC_CMD_CTRL_TYPE(fv) \
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(MAKEF_VAR(CRG_U3DC_CMD_CTRL_TYPE, (fv)))
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#define CRG_U3DC_CMD_CTRL_STATUS_SHIFT (16)
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#define CRG_U3DC_CMD_CTRL_STATUS_MASK \
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(0xf<<CRG_U3DC_CMD_CTRL_STATUS_SHIFT)
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#define CRG_U3DC_CMD_CTRL_STATUS(fv) \
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(MAKEF_VAR(CRG_U3DC_CMD_CTRL_STATUS, (fv)))
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#define CRG_U3DC_CMD_CTRL_STATUS_GET(v) \
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(GETF(CRG_U3DC_CMD_CTRL_STATUS, (v)))
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#define CRG_U3DC_CMD_INIT_EP0 (0L)
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#define CRG_U3DC_CMD_UPDATE_EP0 (1L)
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#define CRG_U3DC_CMD_SET_ADDRESS (2L)
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#define CRG_U3DC_CMD_SEND_DEV_NOTIFY (3L)
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#define CRG_U3DC_CMD_CONFIG_EP (4L)
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#define CRG_U3DC_CMD_SET_HALT (5L)
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#define CRG_U3DC_CMD_CLR_HALT (6L)
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#define CRG_U3DC_CMD_RST_SEQNUM (7L)
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#define CRG_U3DC_CMD_STOP_EP (8L)
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#define CRG_U3DC_CMD_SET_TR_DQPTR (9L)
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#define CRG_U3DC_CMD_FORCE_FLOW_CTRL (10L)
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#define CRG_U3DC_CMD_REQ_LDM_EXCHAG (11L)
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/* int register*/
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/* iman bits*/
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#define CRG_U3DC_IMAN_INT_PEND (1L << 0)
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#define CRG_U3DC_IMAN_INT_EN (1L << 1)
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/* erdp bits*/
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#define CRG_U3DC_ERDPLO_EHB (1 << 3)
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#define CRG_U3DC_ERDPLO_ADDRLO(fv) ((fv) & 0xfffffff0)
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/**/
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/*command params*/
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/*command0 init ep0*/
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#define CRG_CMD0_0_DQPTRLO_SHIFT (4)
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#define CRG_CMD0_0_DQPTRLO_MASK \
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(0x0fffffff << CRG_CMD0_0_DQPTRLO_SHIFT)
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#define CRG_CMD0_0_DCS_SHIFT (0)
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#define CRG_CMD0_0_DCS_MASK (0x1 << CRG_CMD0_0_DCS_SHIFT)
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#define CRG_CMD0_0_DCS(fv) (MAKEF_VAR(CRG_CMD0_0_DCS, (fv)))
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/*command1 update ep0 */
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#define CRG_CMD1_0_MPS_SHIFT (16)
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#define CRG_CMD1_0_MPS_MASK (0xffff << CRG_CMD1_0_MPS_SHIFT)
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#define CRG_CMD1_0_MPS(fv) (MAKEF_VAR(CRG_CMD1_0_MPS, (fv)))
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/*command2 set addr */
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#define CRG_CMD2_0_DEV_ADDR_SHIFT (0)
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#define CRG_CMD2_0_DEV_ADDR_MASK (0xff << CRG_CMD2_0_DEV_ADDR_SHIFT)
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#define CRG_CMD2_0_DEV_ADDR(fv) (MAKEF_VAR(CRG_CMD2_0_DEV_ADDR, (fv)))
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/*command type*/
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enum crg_cmd_type {
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CRG_CMD_INIT_EP0 = 0,
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CRG_CMD_UPDATE_EP0_CFG = 1,
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CRG_CMD_SET_ADDR = 2,
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CRG_CMD_SEND_DEV_NOTIFICATION = 3,
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CRG_CMD_CONFIG_EP = 4,
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CRG_CMD_SET_HALT = 5,
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CRG_CMD_CLEAR_HALT = 6,
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CRG_CMD_RESET_SEQNUM = 7,
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CRG_CMD_STOP_EP = 8,
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CRG_CMD_SET_TR_DQPTR = 9,
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CRG_CMD_FORCE_FLOW_CONTROL = 10,
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CRG_CMD_REQ_LDM_EXCHANGE = 11
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};
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#define reg_read readl
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#define reg_write(a, v) writel(v, a)
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struct crg_gadget_dev;
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extern struct crg_gadget_dev *
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crg_gadget_init(void __iomem *udc_mmio_base, int controller_index);
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extern int crg_gadget_remove(struct crg_gadget_dev *crg_udc);
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struct crg_udc_platdata {
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int num_out_eps;
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int num_in_eps;
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};
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int usb_gadget_register_driver(struct usb_gadget_driver *drive);
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int g_dnl_board_usb_cable_connected(void);
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#endif /* __CRG_UDC_H__ */
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