118 lines
4.2 KiB
C
118 lines
4.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __DT_BINDINGS_CLOCK_SC2_H
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#define __DT_BINDINGS_CLOCK_SC2_H
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/*
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* CLKID index values
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*/
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#define CLKID_XTAL 0
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#define CLKID_FIXED_PLL 1
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#define CLKID_FCLK_DIV2 2
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#define CLKID_FCLK_DIV3 3
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#define CLKID_FCLK_DIV5 4
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#define CLKID_FCLK_DIV7 5
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#define CLKID_FCLK_DIV2P5 6
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#define CLKID_FCLK_DIV4 7
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#define CLKID_SYS_CLK 8
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#define CLKID_SYS_PLL 9
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#define CLKID_SD_EMMC_A_XTAL_GATE 10
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#define CLKID_SD_EMMC_B_XTAL_GATE 11
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#define CLKID_SD_EMMC_C_XTAL_GATE 12
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#define CLKID_GATE_BASE 13
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#define CLKID_SPIFC_XTAL_GATE (CLKID_GATE_BASE + 0)
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#define CLKID_SPIFC_GATE (CLKID_GATE_BASE + 1)
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#define CLKID_SYS_SPIFC (CLKID_GATE_BASE + 2)
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#define CLKID_SAR_ADC_GATE (CLKID_GATE_BASE + 3)
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#define CLKID_SPICC_A_GATE (CLKID_GATE_BASE + 4)
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#define CLKID_SPICC_B_GATE (CLKID_GATE_BASE + 5)
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#define CLKID_SD_EMMC_B_GATE (CLKID_GATE_BASE + 6)
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#define CLKID_SD_EMMC_C_GATE (CLKID_GATE_BASE + 7)
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#define CLKID_SD_EMMC_A_GATE (CLKID_GATE_BASE + 8)
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#define CLKID_MUX_BASE (CLKID_GATE_BASE + 9)
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#define CLKID_SPIFC_MUX (CLKID_MUX_BASE + 0)
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#define CLKID_SARADC_MUX (CLKID_MUX_BASE + 1)
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#define CLKID_SPICC_A_MUX (CLKID_MUX_BASE + 2)
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#define CLKID_SPICC_B_MUX (CLKID_MUX_BASE + 3)
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#define CLKID_SD_EMMC_B_MUX (CLKID_MUX_BASE + 4)
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#define CLKID_SD_EMMC_C_MUX (CLKID_MUX_BASE + 5)
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#define CLKID_SD_EMMC_A_MUX (CLKID_MUX_BASE + 6)
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#define CLKID_DIV_BASE (CLKID_MUX_BASE + 7)
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#define CLKID_SPIFC_DIV (CLKID_DIV_BASE + 0)
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#define CLKID_SARADC_DIV (CLKID_DIV_BASE + 1)
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#define CLKID_SPICC_A_DIV (CLKID_DIV_BASE + 2)
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#define CLKID_SPICC_B_DIV (CLKID_DIV_BASE + 3)
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#define CLKID_SD_EMMC_B_DIV (CLKID_DIV_BASE + 4)
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#define CLKID_SD_EMMC_C_DIV (CLKID_DIV_BASE + 5)
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#define CLKID_SD_EMMC_A_DIV (CLKID_MUX_BASE + 6)
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/* CLKTREE_SYS_CLK_EN0 gates*/
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#define GATE_BASE0 (CLKID_DIV_BASE + 7)
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#define CLKID_CLKTREE (GATE_BASE0 + 0)
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#define CLKID_RESET_CTRL (GATE_BASE0 + 1)
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#define CLKID_ANALOG_CTRL (GATE_BASE0 + 2)
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#define CLKID_PWR_CTRL (GATE_BASE0 + 3)
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#define CLKID_PAD_CTRL (GATE_BASE0 + 4)
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#define CLKID_SYS_CTRL (GATE_BASE0 + 5)
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#define CLKID_TEMP_SENSOR (GATE_BASE0 + 6)
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#define CLKID_AM2AXI_DIV (GATE_BASE0 + 7)
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#define CLKID_SPICC_B (GATE_BASE0 + 8)
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#define CLKID_SPICC_A (GATE_BASE0 + 9)
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#define CLKID_CLK_MSR (GATE_BASE0 + 10)
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#define CLKID_AUDIO (GATE_BASE0 + 11)
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#define CLKID_JTAG_CTRL (GATE_BASE0 + 12)
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#define CLKID_SARADC (GATE_BASE0 + 13)
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#define CLKID_PWM_EF (GATE_BASE0 + 14)
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#define CLKID_PWM_CD (GATE_BASE0 + 15)
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#define CLKID_PWM_AB (GATE_BASE0 + 16)
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#define CLKID_CEC (GATE_BASE0 + 17)
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#define CLKID_I2C_S (GATE_BASE0 + 18)
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#define CLKID_IR_CTRL (GATE_BASE0 + 19)
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#define CLKID_I2C_M_D (GATE_BASE0 + 20)
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#define CLKID_I2C_M_C (GATE_BASE0 + 21)
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#define CLKID_I2C_M_B (GATE_BASE0 + 22)
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#define CLKID_I2C_M_A (GATE_BASE0 + 23)
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#define CLKID_ACODEC (GATE_BASE0 + 24)
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#define CLKID_OTP (GATE_BASE0 + 25)
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#define CLKID_SD_EMMC_A (GATE_BASE0 + 26)
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#define CLKID_USB_PHY (GATE_BASE0 + 27)
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#define CLKID_USB_CTRL (GATE_BASE0 + 28)
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#define CLKID_SYS_DSPB (GATE_BASE0 + 29)
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#define CLKID_SYS_DSPA (GATE_BASE0 + 30)
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#define CLKID_DMA (GATE_BASE0 + 31)
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/* CLKTREE_SYS_CLK_EN1 gates*/
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#define GATE_BASE1 (GATE_BASE0 + 32)
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#define CLKID_IRQ_CTRL (GATE_BASE1 + 0)
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#define CLKID_NIC (GATE_BASE1 + 1)
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#define CLKID_GIC (GATE_BASE1 + 2)
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#define CLKID_UART_C (GATE_BASE1 + 3)
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#define CLKID_UART_B (GATE_BASE1 + 4)
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#define CLKID_UART_A (GATE_BASE1 + 5)
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#define CLKID_SYS_PSRAM (GATE_BASE1 + 6)
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#define CLKID_RSA (GATE_BASE1 + 7)
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#define CLKID_CORESIGHT (GATE_BASE1 + 8)
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/* CLKTREE_AXI_CLK_EN gates */
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#define GATE_BASE2 (GATE_BASE1 + 9)
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#define CLKID_AM2AXI_VAD (GATE_BASE2 + 0)
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#define CLKID_AUDIO_VAD (GATE_BASE2 + 1)
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#define CLKID_AXI_DMC (GATE_BASE2 + 2)
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#define CLKID_AXI_PSRAM (GATE_BASE2 + 3)
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#define CLKID_RAMB (GATE_BASE2 + 4)
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#define CLKID_RAMA (GATE_BASE2 + 5)
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#define CLKID_AXI_SPIFC (GATE_BASE2 + 6)
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#define CLKID_AXI_NIC (GATE_BASE2 + 7)
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#define CLKID_AXI_DMA (GATE_BASE2 + 8)
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#define CLKID_CPU_CTRL (GATE_BASE2 + 9)
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#define CLKID_ROM (GATE_BASE2 + 10)
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#define CLKID_PROC_I2C (GATE_BASE2 + 11)
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#define CLKID_UNREALIZED 100
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#endif /* __SC2_CLKC_H */
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