291 lines
12 KiB
C
291 lines
12 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __DT_BINDINGS_CLOCK_G12A_H
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#define __DT_BINDINGS_CLOCK_G12A_H
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/*
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* CLKID index values
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*/
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//#define CLKID_SYS_PLL 0
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#define CLKID_XTAL 0
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#define CLKID_FIXED_PLL 1
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#define CLKID_FCLK_DIV2 2
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#define CLKID_FCLK_DIV3 3
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#define CLKID_FCLK_DIV4 4
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#define CLKID_FCLK_DIV5 5
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#define CLKID_FCLK_DIV7 6
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#define CLKID_GP0_PLL 7
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#define CLKID_HIFI_PLL 8
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#define CLKID_MPEG_SEL 9
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#define CLKID_MPEG_DIV 10
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#define CLKID_CLK81 11
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#define CLKID_MPLL0 12
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#define CLKID_MPLL1 13
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#define CLKID_MPLL2 14
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#define CLKID_MPLL3 15
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#define CLKID_CPU_FCLK_P00 16
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#define CLKID_CPU_FCLK_P01 17
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#define CLKID_CPU_FCLK_P0 18
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#define CLKID_CPU_FCLK_P10 19
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#define CLKID_CPU_FCLK_P11 20
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#define CLKID_CPU_FCLK_P1 21
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#define CLKID_CPU_FCLK_P 22
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#define CLKID_CPU_CLK 23
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#define CLKID_PCIE_PLL 24
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#define CLKID_PCIE_MUX 25
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#define CLKID_PCIE_REF 26
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#define CLKID_PCIE_INPUT_GATE 27
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#define CLKID_PCIE_CML_EN0 28
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#define CLKID_PCIE_CML_EN1 29
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#define CLKID_MIPI_ENABLE_GATE 30
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#define CLKID_MIPI_BANDGAP_GATE 31
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#define CLKID_FCLK_DIV2P5 32
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/*HHI_GCLK_MPEG0: 0x50*/
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#define GATE_BASE0 33
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#define CLKID_DDR (GATE_BASE0 + 0)
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#define CLKID_DOS (GATE_BASE0 + 1)
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#define CLKID_AUDIO_LOCKER (GATE_BASE0 + 2)
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#define CLKID_MIPI_DSI_HOST (GATE_BASE0 + 3)
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#define CLKID_ETH_PHY (GATE_BASE0 + 4)
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#define CLKID_ISA (GATE_BASE0 + 5)
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#define CLKID_PL301 (GATE_BASE0 + 6)
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#define CLKID_PERIPHS (GATE_BASE0 + 7)
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#define CLKID_SPICC0 (GATE_BASE0 + 8)
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#define CLKID_I2C (GATE_BASE0 + 9)
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#define CLKID_SANA (GATE_BASE0 + 10)
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#define CLKID_SD (GATE_BASE0 + 11)
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#define CLKID_RNG0 (GATE_BASE0 + 12)
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#define CLKID_UART0 (GATE_BASE0 + 13)
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#define CLKID_SPICC1 (GATE_BASE0 + 14)
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#define CLKID_HIU_REG (GATE_BASE0 + 15)
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#define CLKID_MIPI_DSI_PHY (GATE_BASE0 + 16)
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#define CLKID_ASSIST_MISC (GATE_BASE0 + 17)
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#define CLKID_SD_EMMC_A (GATE_BASE0 + 18)
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#define CLKID_SD_EMMC_B (GATE_BASE0 + 19)
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#define CLKID_SD_EMMC_C (GATE_BASE0 + 20)
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#define CLKID_ACODEC (GATE_BASE0 + 21)
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/*HHI_GCLK_MPEG1: 0x51*/
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#define GATE_BASE1 (GATE_BASE0 + 22)
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#define CLKID_AUDIO (GATE_BASE1 + 0)
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#define CLKID_ETH_CORE (GATE_BASE1 + 1)
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#define CLKID_DEMUX (GATE_BASE1 + 2)
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#define CLKID_AIFIFO (GATE_BASE1 + 3)
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#define CLKID_ADC (GATE_BASE1 + 4)
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#define CLKID_UART1 (GATE_BASE1 + 5)
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#define CLKID_G2D (GATE_BASE1 + 6)
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#define CLKID_RESET (GATE_BASE1 + 7)
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#define CLKID_PCIE_COMB (GATE_BASE1 + 8)
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#define CLKID_DOS_PARSER (GATE_BASE1 + 9)
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#define CLKID_USB_GENERAL (GATE_BASE1 + 10)
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#define CLKID_PCIE_PHY (GATE_BASE1 + 11)
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#define CLKID_AHB_ARB0 (GATE_BASE1 + 12)
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/*HHI_GCLK_MPEG2: 0x52*/
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#define GATE_BASE2 (GATE_BASE1 + 13)
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#define CLKID_AHB_DATA_BUS (GATE_BASE2 + 0)
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#define CLKID_AHB_CTRL_BUS (GATE_BASE2 + 1)
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#define CLKID_HTX_HDCP22 (GATE_BASE2 + 2)
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#define CLKID_HTX_PCLK (GATE_BASE2 + 3)
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#define CLKID_BT656 (GATE_BASE2 + 4)
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#define CLKID_USB1_TO_DDR (GATE_BASE2 + 5)
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#define CLKID_MMC_PCLK (GATE_BASE2 + 6)
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#define CLKID_UART2 (GATE_BASE2 + 7)
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#define CLKID_VPU_INTR (GATE_BASE2 + 8)
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#define CLKID_GIC (GATE_BASE2 + 9)
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/*HHI_GCLK_OTHER: 0x54*/
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#define GATE_BASE3 (GATE_BASE2 + 10)
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#define CLKID_VCLK2_VENCI0 (GATE_BASE3 + 0)
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#define CLKID_VCLK2_VENCI1 (GATE_BASE3 + 1)
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#define CLKID_VCLK2_VENCP0 (GATE_BASE3 + 2)
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#define CLKID_VCLK2_VENCP1 (GATE_BASE3 + 3)
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#define CLKID_VCLK2_VENCT0 (GATE_BASE3 + 4)
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#define CLKID_VCLK2_VENCT1 (GATE_BASE3 + 5)
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#define CLKID_VCLK2_OTHER (GATE_BASE3 + 6)
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#define CLKID_VCLK2_ENCI (GATE_BASE3 + 7)
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#define CLKID_VCLK2_ENCP (GATE_BASE3 + 8)
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#define CLKID_DAC_CLK (GATE_BASE3 + 9)
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#define CLKID_AOCLK_GATE (GATE_BASE3 + 10)
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#define CLKID_IEC958_GATE (GATE_BASE3 + 11)
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#define CLKID_ENC480P (GATE_BASE3 + 12)
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#define CLKID_RNG1 (GATE_BASE3 + 13)
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#define CLKID_VCLK2_ENCT (GATE_BASE3 + 14)
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#define CLKID_VCLK2_ENCL (GATE_BASE3 + 15)
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#define CLKID_VCLK2_VENCLMMC (GATE_BASE3 + 16)
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#define CLKID_VCLK2_VENCL (GATE_BASE3 + 17)
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#define CLKID_VCLK2_OTHER1 (GATE_BASE3 + 18)
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/*HHI_GCLK_SP_MPEG: 0x55*/
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#define GATE_BASE4 (GATE_BASE3 + 19)
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#define CLKID_EFUSE (GATE_BASE4 + 0)
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#define GATE_AO_BASE (GATE_BASE4 + 1)
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#define CLKID_AO_MEDIA_CPU (GATE_AO_BASE + 0)
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#define CLKID_AO_AHB_SRAM (GATE_AO_BASE + 1)
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#define CLKID_AO_AHB_BUS (GATE_AO_BASE + 2)
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#define CLKID_AO_IFACE (GATE_AO_BASE + 3)
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#define CLKID_AO_I2C (GATE_AO_BASE + 4)
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#define OTHER_BASE (GATE_AO_BASE + 5)
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#define CLKID_SD_EMMC_A_P0_MUX (OTHER_BASE + 0)
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#define CLKID_SD_EMMC_A_P0_DIV (OTHER_BASE + 1)
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#define CLKID_SD_EMMC_A_P0_GATE (OTHER_BASE + 2)
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#define CLKID_SD_EMMC_A_P0_COMP (OTHER_BASE + 3)
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#define CLKID_SD_EMMC_B_P0_MUX (OTHER_BASE + 4)
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#define CLKID_SD_EMMC_B_P0_DIV (OTHER_BASE + 5)
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#define CLKID_SD_EMMC_B_P0_GATE (OTHER_BASE + 6)
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#define CLKID_SD_EMMC_B_P0_COMP (OTHER_BASE + 7)
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#define CLKID_SD_EMMC_C_P0_MUX (OTHER_BASE + 8)
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#define CLKID_SD_EMMC_C_P0_DIV (OTHER_BASE + 9)
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#define CLKID_SD_EMMC_C_P0_GATE (OTHER_BASE + 10)
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#define CLKID_SD_EMMC_C_P0_COMP (OTHER_BASE + 11)
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#define CLKID_SD_EMMC_B_MUX (OTHER_BASE + 12)
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#define CLKID_SD_EMMC_B_DIV (OTHER_BASE + 13)
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#define CLKID_SD_EMMC_B_GATE (OTHER_BASE + 14)
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#define CLKID_SD_EMMC_B_COMP (OTHER_BASE + 15)
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#define CLKID_SD_EMMC_C_MUX (OTHER_BASE + 16)
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#define CLKID_SD_EMMC_C_DIV (OTHER_BASE + 17)
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#define CLKID_SD_EMMC_C_GATE (OTHER_BASE + 18)
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#define CLKID_SD_EMMC_C_COMP (OTHER_BASE + 19)
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#define CLKID_GPU_BASE (OTHER_BASE + 20)
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#define CLKID_GPU_P0_MUX (CLKID_GPU_BASE + 0)
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#define CLKID_GPU_P0_DIV (CLKID_GPU_BASE + 1)
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#define CLKID_GPU_P0_GATE (CLKID_GPU_BASE + 2)
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#define CLKID_GPU_P0_COMP (CLKID_GPU_BASE + 3)
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#define CLKID_GPU_P1_MUX (CLKID_GPU_BASE + 4)
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#define CLKID_GPU_P1_DIV (CLKID_GPU_BASE + 5)
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#define CLKID_GPU_P1_GATE (CLKID_GPU_BASE + 6)
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#define CLKID_GPU_P1_COMP (CLKID_GPU_BASE + 7)
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#define CLKID_GPU_MUX (CLKID_GPU_BASE + 8)
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#define CLKID_MEDIA_BASE (CLKID_GPU_BASE + 9)
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#define CLKID_VPU_P0_MUX (CLKID_MEDIA_BASE + 0)
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#define CLKID_VPU_P0_DIV (CLKID_MEDIA_BASE + 1)
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#define CLKID_VPU_P0_GATE (CLKID_MEDIA_BASE + 2)
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#define CLKID_VPU_P0_COMP (CLKID_MEDIA_BASE + 3)
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#define CLKID_VPU_P1_MUX (CLKID_MEDIA_BASE + 4)
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#define CLKID_VPU_P1_DIV (CLKID_MEDIA_BASE + 5)
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#define CLKID_VPU_P1_GATE (CLKID_MEDIA_BASE + 6)
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#define CLKID_VPU_P1_COMP (CLKID_MEDIA_BASE + 7)
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#define CLKID_VPU_MUX (CLKID_MEDIA_BASE + 8)
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#define CLKID_VAPB_P0_MUX (CLKID_MEDIA_BASE + 9)
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#define CLKID_VAPB_P0_DIV (CLKID_MEDIA_BASE + 10)
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#define CLKID_VAPB_P0_GATE (CLKID_MEDIA_BASE + 11)
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#define CLKID_VAPB_P0_COMP (CLKID_MEDIA_BASE + 12)
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#define CLKID_VAPB_P1_MUX (CLKID_MEDIA_BASE + 13)
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#define CLKID_VAPB_P1_DIV (CLKID_MEDIA_BASE + 14)
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#define CLKID_VAPB_P1_GATE (CLKID_MEDIA_BASE + 15)
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#define CLKID_VAPB_P1_COMP (CLKID_MEDIA_BASE + 16)
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#define CLKID_VAPB_MUX (CLKID_MEDIA_BASE + 17)
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#define CLKID_GE2D_GATE (CLKID_MEDIA_BASE + 18)
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#define CLKID_DSI_MEAS_MUX (CLKID_MEDIA_BASE + 19)
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#define CLKID_DSI_MEAS_DIV (CLKID_MEDIA_BASE + 20)
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#define CLKID_DSI_MEAS_GATE (CLKID_MEDIA_BASE + 21)
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#define CLKID_DSI_MEAS_COMP (CLKID_MEDIA_BASE + 22)
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#define CLKID_VPU_CLKB_TMP_COMP (CLKID_MEDIA_BASE + 23)
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#define CLKID_VPU_CLKB_COMP (CLKID_MEDIA_BASE + 24)
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#define CLKID_VDEC_P0_MUX (CLKID_MEDIA_BASE + 25)
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#define CLKID_VDEC_P0_DIV (CLKID_MEDIA_BASE + 26)
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#define CLKID_VDEC_P0_GATE (CLKID_MEDIA_BASE + 27)
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#define CLKID_VDEC_P0_COMP (CLKID_MEDIA_BASE + 28)
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#define CLKID_VDEC_P1_MUX (CLKID_MEDIA_BASE + 29)
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#define CLKID_VDEC_P1_DIV (CLKID_MEDIA_BASE + 30)
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#define CLKID_VDEC_P1_GATE (CLKID_MEDIA_BASE + 31)
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#define CLKID_VDEC_P1_COMP (CLKID_MEDIA_BASE + 32)
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#define CLKID_VDEC_MUX (CLKID_MEDIA_BASE + 33)
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#define CLKID_HCODEC_P0_MUX (CLKID_MEDIA_BASE + 34)
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#define CLKID_HCODEC_P0_DIV (CLKID_MEDIA_BASE + 35)
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#define CLKID_HCODEC_P0_GATE (CLKID_MEDIA_BASE + 36)
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#define CLKID_HCODEC_P0_COMP (CLKID_MEDIA_BASE + 37)
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#define CLKID_HCODEC_P1_MUX (CLKID_MEDIA_BASE + 38)
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#define CLKID_HCODEC_P1_DIV (CLKID_MEDIA_BASE + 39)
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#define CLKID_HCODEC_P1_GATE (CLKID_MEDIA_BASE + 40)
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#define CLKID_HCODEC_P1_COMP (CLKID_MEDIA_BASE + 41)
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#define CLKID_HCODEC_MUX (CLKID_MEDIA_BASE + 42)
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/*HEVCB_CLK*/
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#define CLKID_HEVC_P0_MUX (CLKID_MEDIA_BASE + 43)
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#define CLKID_HEVC_P0_DIV (CLKID_MEDIA_BASE + 44)
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#define CLKID_HEVC_P0_GATE (CLKID_MEDIA_BASE + 45)
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#define CLKID_HEVC_P0_COMP (CLKID_MEDIA_BASE + 46)
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#define CLKID_HEVC_P1_MUX (CLKID_MEDIA_BASE + 47)
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#define CLKID_HEVC_P1_DIV (CLKID_MEDIA_BASE + 48)
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#define CLKID_HEVC_P1_GATE (CLKID_MEDIA_BASE + 49)
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#define CLKID_HEVC_P1_COMP (CLKID_MEDIA_BASE + 50)
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#define CLKID_HEVC_MUX (CLKID_MEDIA_BASE + 51)
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/*HEVCF_CLK*/
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#define CLKID_HEVCF_P0_MUX (CLKID_MEDIA_BASE + 52)
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#define CLKID_HEVCF_P0_DIV (CLKID_MEDIA_BASE + 53)
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#define CLKID_HEVCF_P0_GATE (CLKID_MEDIA_BASE + 54)
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#define CLKID_HEVCF_P0_COMP (CLKID_MEDIA_BASE + 55)
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#define CLKID_HEVCF_P1_MUX (CLKID_MEDIA_BASE + 56)
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#define CLKID_HEVCF_P1_DIV (CLKID_MEDIA_BASE + 57)
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#define CLKID_HEVCF_P1_GATE (CLKID_MEDIA_BASE + 58)
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#define CLKID_HEVCF_P1_COMP (CLKID_MEDIA_BASE + 59)
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#define CLKID_HEVCF_MUX (CLKID_MEDIA_BASE + 60)
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#define CLKID_VPU_CLKC_P0_MUX (CLKID_MEDIA_BASE + 61)
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#define CLKID_VPU_CLKC_P0_DIV (CLKID_MEDIA_BASE + 62)
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#define CLKID_VPU_CLKC_P0_GATE (CLKID_MEDIA_BASE + 63)
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#define CLKID_VPU_CLKC_P0_COMP (CLKID_MEDIA_BASE + 64)
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#define CLKID_VPU_CLKC_P1_MUX (CLKID_MEDIA_BASE + 65)
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#define CLKID_VPU_CLKC_P1_DIV (CLKID_MEDIA_BASE + 66)
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#define CLKID_VPU_CLKC_P1_GATE (CLKID_MEDIA_BASE + 67)
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#define CLKID_VPU_CLKC_P1_COMP (CLKID_MEDIA_BASE + 68)
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#define CLKID_VPU_CLKC_MUX (CLKID_MEDIA_BASE + 69)
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#define CLKID_MISC_BASE (CLKID_MEDIA_BASE + 70)
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#define CLKID_SPICC0_MUX (CLKID_MISC_BASE + 0)
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#define CLKID_SPICC0_DIV (CLKID_MISC_BASE + 1)
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#define CLKID_SPICC0_GATE (CLKID_MISC_BASE + 2)
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#define CLKID_SPICC0_COMP (CLKID_MISC_BASE + 3)
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#define CLKID_SPICC1_MUX (CLKID_MISC_BASE + 4)
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#define CLKID_SPICC1_DIV (CLKID_MISC_BASE + 5)
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#define CLKID_SPICC1_GATE (CLKID_MISC_BASE + 6)
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#define CLKID_SPICC1_COMP (CLKID_MISC_BASE + 7)
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#define CLKID_TS_COMP (CLKID_MISC_BASE + 8)
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/*gpio 12M/24M */
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#define CLKID_24M (CLKID_MISC_BASE + 9)
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#define CLKID_12M_DIV (CLKID_MISC_BASE + 10)
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#define CLKID_12M_GATE (CLKID_MISC_BASE + 11)
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/*G12B clk*/
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#define CLKID_G12B_ADD_BASE (CLKID_MISC_BASE + 12)
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#define CLKID_CPUB_FCLK_P (CLKID_G12B_ADD_BASE + 0)
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#define CLKID_CPUB_CLK (CLKID_G12B_ADD_BASE + 1)
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/*G12B gate*/
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#define CLKID_CSI_DIG (CLKID_G12B_ADD_BASE + 2)
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#define CLKID_VIPNANOQ (CLKID_G12B_ADD_BASE + 3)
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#define CLKID_GDC (CLKID_G12B_ADD_BASE + 4)
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#define CLKID_MIPI_ISP (CLKID_G12B_ADD_BASE + 5)
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#define CLKID_CSI2_PHY1 (CLKID_G12B_ADD_BASE + 6)
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#define CLKID_CSI2_PHY0 (CLKID_G12B_ADD_BASE + 7)
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#define CLKID_GDC_CORE_CLK_COMP (CLKID_G12B_ADD_BASE + 8)
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#define CLKID_GDC_AXI_CLK_COMP (CLKID_G12B_ADD_BASE + 9)
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#define CLKID_VNANOQ_CORE_CLK_COMP (CLKID_G12B_ADD_BASE + 10)
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#define CLKID_VNANOQ_AXI_CLK_COMP (CLKID_G12B_ADD_BASE + 11)
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#define CLKID_VNANOQ_MUX (CLKID_G12B_ADD_BASE + 12)
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#define CLKID_MIPI_ISP_CLK_COMP (CLKID_G12B_ADD_BASE + 13)
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#define CLKID_MIPI_CSI_PHY_CLK0_COMP (CLKID_G12B_ADD_BASE + 14)
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#define CLKID_MIPI_CSI_PHY_CLK1_COMP (CLKID_G12B_ADD_BASE + 15)
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#define CLKID_MIPI_CSI_PHY_MUX (CLKID_G12B_ADD_BASE + 16)
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#define CLKID_SYS1_PLL (CLKID_G12B_ADD_BASE + 17)
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#define CLKID_AO_BASE (CLKID_G12B_ADD_BASE + 18)
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#define CLKID_AO_CLK81 (CLKID_AO_BASE + 0)
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#define CLKID_SARADC_MUX (CLKID_AO_BASE + 1)
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#define CLKID_SARADC_DIV (CLKID_AO_BASE + 2)
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#define CLKID_SARADC_GATE (CLKID_AO_BASE + 3)
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#define CLKID_SYS_PLL (CLKID_AO_BASE + 4)
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#define NR_CLKS (CLKID_AO_BASE + 5)
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#endif /* __G12A_CLKC_H */
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