47 lines
1.4 KiB
C
47 lines
1.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __DT_BINDINGS_CLOCK_A4_H
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#define __DT_BINDINGS_CLOCK_A4_H
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/*
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* CLKID index values
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*/
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#define CLKID_XTAL 0
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#define CLKID_FIXED_PLL 1
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#define CLKID_FCLK_DIV2 2
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#define CLKID_FCLK_DIV3 3
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#define CLKID_FCLK_DIV4 4
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#define CLKID_FCLK_DIV5 5
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#define CLKID_FCLK_DIV7 6
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#define CLKID_FCLK_DIV2P5 7
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#define CLKID_SYS_CLK 8
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#define CLKID_SYS_PLL 9
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#define CLKID_GP0_PLL 10
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#define CLKID_GATE_BASE 11
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#define CLKID_SARADC (CLKID_GATE_BASE + 0)
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#define CLKID_SPICC_0 (CLKID_GATE_BASE + 1)
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#define CLKID_SPICC_1 (CLKID_GATE_BASE + 2)
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#define CLKID_SD_EMMC_C (CLKID_GATE_BASE + 3)
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#define CLKID_SD_EMMC_A (CLKID_GATE_BASE + 4)
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#define CLKID_MUX_BASE (CLKID_GATE_BASE + 5)
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#define CLKID_SARADC_SEL (CLKID_MUX_BASE + 0)
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#define CLKID_SPICC_0_SEL (CLKID_MUX_BASE + 1)
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#define CLKID_SPICC_1_SEL (CLKID_MUX_BASE + 2)
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#define CLKID_SD_EMMC_C_SEL (CLKID_MUX_BASE + 3)
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#define CLKID_SD_EMMC_A_SEL (CLKID_MUX_BASE + 4)
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#define CLKID_DIV_BASE (CLKID_MUX_BASE + 5)
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#define CLKID_SARADC_DIV (CLKID_DIV_BASE + 0)
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#define CLKID_SPICC_0_DIV (CLKID_DIV_BASE + 1)
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#define CLKID_SPICC_1_DIV (CLKID_DIV_BASE + 2)
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#define CLKID_SD_EMMC_C_DIV (CLKID_DIV_BASE + 3)
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#define CLKID_SD_EMMC_A_DIV (CLKID_DIV_BASE + 4)
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#define CLKID_UNREALIZED 100
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#endif /* __A4_CLKC_H */
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