115 lines
2.8 KiB
C
115 lines
2.8 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __MESON_SARADC_H__
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#define __MESON_SARADC_H__
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#include <common.h>
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#include <adc.h>
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#include <clk.h>
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enum ADC_CHANNEL_TYPE {
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MESON_SARADC_CH0 = 0,
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MESON_SARADC_CH1,
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MESON_SARADC_CH2,
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MESON_SARADC_CH3,
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MESON_SARADC_CH4,
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MESON_SARADC_CH5,
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MESON_SARADC_CH6,
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MESON_SARADC_CH7,
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MESON_SARADC_CH_MAX,
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};
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enum MESON_SARADC_AVG_MODE {
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NO_AVERAGING = 0x0,
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MEAN_AVERAGING = 0x1,
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MEDIAN_AVERAGING = 0x2,
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};
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enum MESON_SARADC_NUM_SAMPLES {
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ONE_SAMPLE = 0x0,
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TWO_SAMPLES = 0x1,
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FOUR_SAMPLES = 0x2,
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EIGHT_SAMPLES = 0x3,
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};
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enum MESON_SARADC_RESOLUTION {
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SARADC_10BIT = 10,
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SARADC_12BIT = 12,
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SARADC_22BIT = 22,
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};
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enum MESON_SARADC_BIT_STATE {
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BIT_LOW = 0,
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BIT_HIGH = 1,
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};
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struct meson_saradc;
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struct meson_saradc_diff_ops {
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void (*extra_init)(struct meson_saradc *priv);
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void (*set_ch7_mux)(struct meson_saradc *priv, int ch, int mux);
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void (*enable_decim_filter)(struct meson_saradc *priv,
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int ch, unsigned int mode);
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void (*set_ref_voltage)(struct meson_saradc *priv, unsigned int mode,
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int ch);
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int (*get_fifo_channel)(int val);
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int (*get_fifo_data)(struct meson_saradc *priv,
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struct adc_uclass_platdata *uc_pdata, int val);
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};
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/*
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* struct meson_saradc_data - describe the differences of different platform
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*
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* @reg3_ring_counter_disable: to disable continuous ring counter.
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* gxl and later: 1; others(gxtvbb etc): 0
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* @reg11_vref_en: g12a and later: 0; others(axg etc): 1
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* @reg11_vcm_sel: g12a and later: 0; others(axg etc): 1
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* @reg11_eoc: g12a and later: 1; others(axg etc): 0
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* @has_bl30_integration:
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* @update_vref_conf: only for C2 & A5; C2: 0; A5: 1
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* @num_channels: the number of adc channels
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* @self_test_channel: channel of self-test
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* @resolution: gxl and later: 12bit; others(gxtvbb etc): 10bit
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* @clock_rate: saradc clock rate
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*/
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struct meson_saradc_data {
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bool reg3_ring_counter_disable;
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unsigned int reg11_bandgap_en_mask;
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bool reg11_vref_en;
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bool reg11_vcm_sel;
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bool reg11_eoc;
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unsigned int reg13_calib_factor_mask;
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bool has_bl30_integration;
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bool update_vref_conf;
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unsigned char self_test_channel;
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unsigned char num_channels;
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unsigned int resolution;
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const struct meson_saradc_diff_ops *dops;
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unsigned int capacity;
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unsigned long clock_rate;
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};
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struct meson_saradc {
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phys_addr_t base;
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int active_channel;
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unsigned int current_mode;
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struct clk xtal;
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struct clk adc_mux;
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struct clk adc_div;
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struct clk adc_gate;
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struct meson_saradc_data *data;
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bool wk_active;
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};
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extern const struct adc_ops meson_saradc_ops;
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int meson_saradc_probe(struct udevice *dev);
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int meson_saradc_remove(struct udevice *dev);
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int meson_saradc_ofdata_to_platdata(struct udevice *dev);
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#define SARADC_CH_SELF_TEST MESON_SARADC_CH7
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#endif /*_MESON_SARADC_H_*/
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