131 lines
3.7 KiB
C
131 lines
3.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __AMLOGIC_TLV_H_
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#define __AMLOGIC_TLV_H_
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typedef struct __s_bl2_tlv_item_t{
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unsigned int nType; //type: user defined, should sync between BL2 and BL3X
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unsigned int nLength; //length: length of szContent, no alignment
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unsigned int nStoreLength; //length: length of szContent, alignment to 16
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unsigned char szRserved1[4];//reserved for future
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struct __s_bl2_tlv_item_t * pNextItem;//next item, list for fetch all quickly
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unsigned char szContent[4]; //data transfered from BL2
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}s_bl2_tlv_item_t;
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typedef struct __s_bl2_to_bl3x_hdr_t{
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unsigned int nMagic; //magic for identify itself, AML_BL2_TMASTER_MAGIC (@BL2)
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unsigned int nVersion; //version for control
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unsigned int nHeadSize; //sizeof(this)
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unsigned char szRserved1[4]; //reserved for future
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unsigned char szBL2Info[96]; //BL2 build information
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s_bl2_tlv_item_t * pNextBlob; //next active valid blob item
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unsigned int nTLVCount; //current valid TLV item number
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unsigned int nTotalSize; //total size of all TLV items
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unsigned char szSHA2TLV[32]; //SHA2 of all TLV items, size is nTotalSize
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} s_bl2_to_bl3x_hdr_t;
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typedef struct __s_bl2_to_bl3x_send_t{
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s_bl2_to_bl3x_hdr_t hdr;
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unsigned char szSHA2Head[32];
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s_bl2_tlv_item_t blob[1];
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} s_bl2_to_bl3x_send_t;
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typedef enum{
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e_ok_ret = 0,
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e_err_not_support = 0x01,
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e_err_no_item = 0x10,
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e_err_sha_hdr = 0x11,
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e_err_sha_tlv = 0x12,
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e_err_in_data = 0x20,
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e_err_in_size = 0x21,
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e_err_over_size=0x22,
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e_err_item_exit=0x23,
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}e_ret_type;
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typedef enum{
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e_t_ap_ver = 0x10,
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e_t_scp_ver = 0x11,
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e_t_sp_ver = 0x12,
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e_t_bl2z_ver = 0x13,
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e_t_bl30_ver = 0x14,
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e_t_bl301_ver = 0x15,
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e_t_bl31_ver = 0x16,
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e_t_bl32_ver = 0x17,
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e_t_bl33_ver = 0x18,
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e_t_root_aes = 0x20,
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e_t_root_rsa_sha_all = 0x21,
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e_t_root_rsa_sha = 0x22,
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e_t_root_rsa_puk = 0x23,
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e_t_user_aes = 0x30,
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e_t_user_rsa_sha_all = 0x31,
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e_t_user_rsa_sha = 0x32,
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e_t_user_rsa_puk = 0x33,
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e_t_bl30_rsa_puk = 0x50,
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e_t_bl30_aes = 0x51,
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e_t_bl31_rsa_puk = 0x60,
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e_t_bl31_aes = 0x61,
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e_t_bl32_rsa_puk = 0x70,
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e_t_bl32_aes = 0x71,
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e_t_bl33_rsa_puk = 0x80,
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e_t_bl33_aes = 0x81,
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//....
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}e_item_type;
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//magic ID
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#define AML_BL2_TMASTER_MAGIC (0x324c4240) //@BL2
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//major & minor version
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#define AML_BL2_TMASTER_MAJ_VER (0x00) //major version
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#define AML_BL2_TMASTER_MIN_VER (0x01) //minor version
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#define AML_BL2_TMASTER_VERSION ((AML_BL2_TMASTER_MAJ_VER << 16) |\
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AML_BL2_TMASTER_MIN_VER) //major << 16 | minor version
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//item data length alignment
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#define AML_BL2_TMASTER_ITEM_UNIT_LEN (16)
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#define AML_BL2_TMASTER_ITEM_ALIGN_LEN(len) ((len) + (AML_BL2_TMASTER_ITEM_UNIT_LEN-1)) & (~(AML_BL2_TMASTER_ITEM_UNIT_LEN-1))
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//CFG reg to store DDR address
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#define AML_BL2_TMASTER_CFG_REG (AO_SEC_GP_CFG6)
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//DDR buffer size
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#ifndef AML_BL2_TMASTER_DDR_MLEN
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#define AML_BL2_TMASTER_DDR_MLEN ((1<<20) - sizeof(s_bl2_to_bl3x_send_t)) //1MB for transfer data from BL2 to BL3X
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#endif
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//flag to pass BL2 build info to BL3X
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//#define CONFIG_AML_TLV_BL2_VER_INFO
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//IMPORTANT: BECAUSE THOSE FUNCTIONS WILL USE DDR AS STORAGE(DEFAULT) THEN
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// ALL THE APIS MUST BE USED AFTER DDR INIT DONE
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//global APIs to pad & fetch item
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//pad item with data, type and length
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e_ret_type aml_append_item(unsigned int nType, unsigned int nLength, unsigned char *pData);
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//fetch item with type
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e_ret_type aml_fetch_item(unsigned int nType, s_bl2_tlv_item_t **ppItem);
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#endif /* __AMLOGIC_TLV_H_ */
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