424 lines
11 KiB
C
424 lines
11 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#include "nfc.h"
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#include "page_info.h"
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struct nfc_clk_provider clk_provider[MAX_CLK_PROVIDER] = {
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{OSC_CLK_24MHZ, CLK_6MHZ, 1, 4, 0, 1},
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{OSC_CLK_24MHZ, CLK_12MHZ, 1, 2, 0, 2},
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{FIX_PLL_DIV2, CLK_20MHZ, 12, 4, 0, 3},
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{FIX_PLL_DIV2, CLK_41MHZ, 6, 4, 0, 5},
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{FIX_PLL_DIV2, CLK_83MHZ, 3, 4, 0, 7},
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{FIX_PLL_DIV2P5, CLK_100MHZ_400, 2, 4, 0, 11},
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{FIX_PLL_DIV2, CLK_100MHZ_500, 2, 5, 0, 11},
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{FIX_PLL_DIV2, CLK_125MHZ, 2, 4, 0, 13},
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{FIX_PLL_DIV2P5, CLK_133MHZ, 2, 3, 0, 13},
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{FIX_PLL_DIV2, CLK_166MHZ_333, 3, 2, 0, 15},
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{FIX_PLL_DIV3, CLK_166MHZ_666, 1, 4, 0, 15},
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{FIX_PLL_DIV2P5, CLK_200MHZ_400, 2, 2, 0, 21},
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{FIX_PLL_DIV2P5, CLK_200MHZ_800, 1, 4, 0, 21},
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};
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struct nfc_clk_provider *g_clk_info = &clk_provider[CLK_83MHZ];
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void nfc_pinmux_init(enum NFC_STORAGE_TYPE storage_type)
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{
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unsigned int value;
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/*
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* Bit2 of PADCTRL_MISC_CTRL0: spi_nand_sel_pad
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* spi_nand_sel_pad == 1, the spi pinmux should select func4.
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* spi_nand_sel_pad == 0, the spi pinmux should select func1. but it
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* maybe have riskiness
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*/
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switch (storage_type) {
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case SPINAND_FLASH:
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case SPINOR_FLASH:
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/* d0-7 and cs pull up; clk pull down */
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writel(readl(PADCTRL_GPIOB_PULL_EN) | 0x24FF,
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PADCTRL_GPIOB_PULL_UP);
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value = readl(PADCTRL_GPIOB_PULL_UP) & (~0x24FF);
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writel(value | 0x20FF, PADCTRL_GPIOB_PULL_UP);
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writel(0x44444444, PADCTRL_PIN_MUX_REG0);
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value = readl(PADCTRL_PIN_MUX_REG1) & (~0x00F00F00);
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writel(value | 0x00400400, PADCTRL_PIN_MUX_REG1);
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break;
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#ifdef CONFIG_BOOT_SPI_NAND
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case SLCNAND_FLASH:
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writel(readl(PADCTRL_GPIOB_PULL_EN) | 0xFFFF,
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PADCTRL_GPIOB_PULL_EN);
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writel(0xF500, PADCTRL_GPIOB_PULL_UP);
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writel(0x11111111, PADCTRL_PIN_MUX_REG0);
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writel(0x22222, PADCTRL_PIN_MUX_REG1);
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break;
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#endif
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default:
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break;
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}
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}
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void nfc_send_idle(uint32_t cycle)
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{
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writel(CE0 | IDLE | cycle, NAND_CMD);
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}
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void nfc_deselect_chip(uint32_t cycle)
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{
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writel(CEF | IDLE | cycle, NAND_CMD);
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}
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void nfc_select_mode(int spi_mode)
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{
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unsigned int value = 0;
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if (spi_mode) {
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value = readl(SPI_CFG);
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value |= (1 << 31);
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}
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writel(value, SPI_CFG);
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}
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unsigned int nfc_recalculate_n2m_command(uint32_t size, int no_cal)
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{
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uint32_t n2m_cmd, page_size;
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int ecc_size;
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page_size = page_info_get_page_size();
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n2m_cmd = page_info_get_n2m_command();
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if (no_cal)
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return n2m_cmd;
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if (size == page_size)
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return n2m_cmd;
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ecc_size = (GET_BCH_MODE(n2m_cmd) == 1) ? 512 : 1024;
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size = (size + ecc_size - 1) & (~(ecc_size - 1));
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n2m_cmd &= ~0x3F;
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while (size >= ecc_size) {
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n2m_cmd++;
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size -= ecc_size;
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}
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return n2m_cmd;
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}
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int nfc_wait_command_fifo_done(uint32_t timeout, int repeat_rb)
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{
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unsigned int t0 = get_timer(0), value;
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while (get_timer(t0) < timeout) {
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value = readl(NAND_CMD);
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if (((value >> 22) & 0x1f) == 0)
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return 0;
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if (repeat_rb && ((value >> 27) & 0x01))
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return ERR_NFC_TIMEOUT;
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}
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return ERR_NFC_TIMEOUT;
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}
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void nfc_raw_size_ext_convert(uint32_t size)
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{
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unsigned int raw_ext;
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raw_ext = readl(SPI_CFG);
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raw_ext &= ~(0xFFF << 18);
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raw_ext |= ((size >> NFC_RAW_CHUNK_SHIFT) << 18);
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writel(raw_ext, SPI_CFG);
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NFC_Print("SPI_CFG", readl(SPI_CFG));
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}
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#define is_fixpll_locked() (1)
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#define IS_FEAT_EN_83MHZ_SPI() (0)
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#define IS_FEAT_EN_41MHZ_SPI() (1)
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#define IS_FEAT_EN_25MHZ_NAND() (1)
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#define otp_get_nfc_rxadj(x) ((*(x)) = 0)
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static struct nfc_clk_provider *nfc_get_clock_provider(int init_stage,
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enum NFC_STORAGE_TYPE storage_type)
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{
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struct nfc_clk_provider *clk_info;
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unsigned char frequency_idx, cs_deselect_time;
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uint32_t line_delay1, line_delay2;
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if (storage_type == SLCNAND_FLASH) {
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clk_info = &clk_provider[CLK_6MHZ];
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if (is_fixpll_locked() && IS_FEAT_EN_25MHZ_NAND())
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clk_info = &clk_provider[CLK_20MHZ];
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goto _exit_get_clk;
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}
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cs_deselect_time = page_info_get_cs_deselect_time();
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frequency_idx = page_info_get_frequency_index();
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if (init_stage || frequency_idx == 0xFF) {
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if (!is_fixpll_locked())
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clk_info = &clk_provider[CLK_12MHZ];
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else if (IS_FEAT_EN_83MHZ_SPI())
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clk_info = &clk_provider[CLK_83MHZ];
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else if (IS_FEAT_EN_41MHZ_SPI())
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clk_info = &clk_provider[CLK_41MHZ];
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else
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clk_info = &clk_provider[CLK_20MHZ];
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otp_get_nfc_rxadj(&clk_info->adj);
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} else {
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line_delay1 = page_info_get_line_delay1();
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line_delay2 = page_info_get_line_delay2();
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clk_info = &clk_provider[frequency_idx & 0x7F];
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clk_info->adj = page_info_get_adj_index();
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if (frequency_idx & 0x80) {
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clk_info->div1 = page_info_get_core_div();
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clk_info->div2 = page_info_get_bus_cycle();
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}
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writel(line_delay1, SD_EMMC_DLY1);
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writel(line_delay2, SD_EMMC_DLY2);
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}
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if (cs_deselect_time != 0xFF) {
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clk_info->cs_deselect_time = cs_deselect_time;
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NFC_Print("clk_info->cs_deselect_time", clk_info->cs_deselect_time);
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}
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_exit_get_clk:
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g_clk_info = clk_info;
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return clk_info;
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}
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void nfc_set_clock_and_timing(int init_stage, enum NFC_STORAGE_TYPE storage_type)
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{
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struct nfc_clk_provider *clk_info;
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unsigned char data_lanes, cmd_lanes, addr_lanes, mode;
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uint32_t value;
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setbits_le32(CLKCTRL_SYS_CLK_EN0_REG0,
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CTRL_NAND_CLK_GATE_ON_BIT);
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setbits_le32(CLKCTRL_NAND_CLK_CTRL,
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CTRL_SDEMMC_CLK_CTRL_ON_BIT);
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clk_info = nfc_get_clock_provider(init_stage, storage_type);
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NFC_Print("clock_index", clk_info->clk_rate);
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value = CLK_DEF_CORE_PHASE | CLK_ALWAYS_ON | CLK_SELECT_NAND;
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value |= clk_info->div1;
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if (clk_info->clk_src_type == FIX_PLL_DIV2) {
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value |= (1 << 6);
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writel(value, SD_EMMC_CLK);
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} else {
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value &= ~(3 << 6);
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writel(value, SD_EMMC_CLK);
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setbits_le32(CLKCTRL_NAND_CLK_CTRL,
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clk_info->clk_src_type << 9);
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}
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if (storage_type != SLCNAND_FLASH) {
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data_lanes = page_info_get_data_lanes_mode();
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cmd_lanes = page_info_get_cmd_lanes_mode();
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addr_lanes = page_info_get_addr_lanes_mode();
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mode = page_info_get_work_mode();
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writel(data_lanes | (cmd_lanes << 2) |
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((clk_info->adj & 0x0F) << 4) |
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(3 << 12) | (mode << 14) | (addr_lanes << 16) |
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(1 << 31), SPI_CFG);
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writel((clk_info->div2 - 1) | (3 << 5) | (1 << 31), NAND_CFG);
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} else {
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writel(clk_info->div2 | (3 << 5) | (1 << 31), NAND_CFG);
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}
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NFC_Print("SPI_CFG", readl(SPI_CFG));
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NFC_Print("NAND_CFG", readl(NAND_CFG));
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NFC_Print("SD_EMMC_CLK", readl(SD_EMMC_CLK));
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NFC_Print("CLKCTRL_NAND_CLK_CTRL", readl(CLKCTRL_NAND_CLK_CTRL));
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}
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void nfc_set_data_bus_width(int bus_width)
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{
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uint32_t spi_cfg = readl(SPI_CFG);
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spi_cfg &= (~0x03);
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spi_cfg |= bus_width;
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writel(spi_cfg, SPI_CFG);
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NFC_Print("SPI_CFG", readl(SPI_CFG));
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}
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uint32_t nfc_send_cmd_addr_and_wait(unsigned char cmd_bitmap, uint8_t cmd,
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uint8_t *addr, uint8_t addr_len,
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uint8_t *data, uint8_t data_len,
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unsigned short state_dummy_ctl)
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{
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uint8_t *buffer = data, dummy_cycles = 0, com_cmd;
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enum CMD_TYPE cmd_type;
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enum STATE_AND_DUMMY_CTL action;
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int i = 0, j = 0, ret;
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if (((cmd_bitmap & TYPE_ADDR) && !addr) ||
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((cmd_bitmap & TYPE_DATA_DRD) && !buffer) ||
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((cmd_bitmap & TYPE_DATA_DWR) && !buffer) ||
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cmd_bitmap == 0)
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return ERR_NFC_WRONG_PARAM;
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action = (state_dummy_ctl >> STATE_AND_DUMMY_CTL_BIT_SHIFT);
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NFC_Print("cs_deselect_time", g_clk_info->cs_deselect_time);
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writel(CEF | IDLE | g_clk_info->cs_deselect_time, NAND_CMD);
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while (cmd_bitmap != 0 && i < 8) {
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cmd_type = CMD_BITMAP_TEST_AND_GET_BIT_VALUE(cmd_bitmap, i);
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CMD_BITMAP_CLEAR_BIT(cmd_bitmap, i);
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switch (cmd_type) {
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case TYPE_NONE:
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/* skip the zero */
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break;
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case TYPE_CMD:
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NFC_Print("TYPE_CMD", CE0 | CLE | cmd);
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if (action & DONT_SEND_CEF) {
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com_cmd = ~cmd;
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NFC_Print("TYPE_CMD", CE0 | CLE | com_cmd);
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writel(CE0 | CLE | com_cmd, NAND_CMD);
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}
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writel(CE0 | CLE | cmd, NAND_CMD);
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break;
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case TYPE_ADDR:
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if (state_dummy_ctl & 0xFF)
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dummy_cycles = (state_dummy_ctl & 0xFF) - 1;
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NFC_Print("dummy_cycles", dummy_cycles);
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if (action & DUMMY_BEFORE_ADDRESS)
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writel(CE0 | DUMMY | dummy_cycles, NAND_CMD);
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addr += addr_len - 1;
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for (j = 0; j < addr_len; j++, addr--) {
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NFC_Print("TYPE_ADDR", CE0 | ALE | *addr);
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writel(CE0 | ALE | *addr, NAND_CMD);
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}
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if (action & DUMMY_AFTER_ADDRESS)
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writel(CE0 | DUMMY | dummy_cycles, NAND_CMD);
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break;
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case TYPE_DATA_DRD:
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NFC_Print("TYPE_DATA_DRD", i);
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for (j = 0; j < data_len; j++, buffer++) {
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writel(CE0 | DRD | 0, NAND_CMD);
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writel(CE0 | IDLE, NAND_CMD);
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writel(CE0 | IDLE, NAND_CMD);
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ret = nfc_wait_command_fifo_done(NFC_COMMAND_FIFIO_TIMEOUT, 0);
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if (ret)
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return ret;
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*buffer = readl(NAND_BUF);
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}
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return 0;
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case TYPE_DATA_DWR:
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NFC_Print("TYPE_DATA_DWR", i);
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for (j = 0; j < data_len; j++, buffer++) {
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writel(CE0 | IDLE | 10, NAND_CMD);
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writel(CE0 | DWR | *buffer, NAND_CMD);
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writel(CE0 | IDLE | 10, NAND_CMD);
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writel(CE0 | IDLE, NAND_CMD);
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writel(CE0 | IDLE, NAND_CMD);
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ret = nfc_wait_command_fifo_done(NFC_COMMAND_FIFIO_TIMEOUT, 0);
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if (ret)
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return ret;
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}
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return 0;
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default:
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break;
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}
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writel(CE0 | IDLE, NAND_CMD);
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i++;
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}
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return nfc_wait_command_fifo_done(NFC_COMMAND_FIFIO_TIMEOUT, 0);
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}
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void nfc_send_repeat_rb_command(void)
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{
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writel(IO6 | RB | 13, NAND_CMD);
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writel(CE0 | IDLE | 2, NAND_CMD);
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writel(CE0 | CLE | 0, NAND_CMD);
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writel(CE0 | IDLE, NAND_CMD);
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writel(CE0 | IDLE, NAND_CMD);
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}
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void nfc_set_dma_mem_and_info(uint32_t mem, unsigned long info)
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{
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uint32_t cmd;
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cmd = GENCMDDADDRL(NFC_CMD_ADL, mem);
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writel(cmd, NAND_CMD);
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cmd = GENCMDDADDRH(NFC_CMD_ADH, mem);
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writel(cmd, NAND_CMD);
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cmd = GENCMDIADDRL(NFC_CMD_AIL, info);
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writel(cmd, NAND_CMD);
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cmd = GENCMDIADDRH(NFC_CMD_AIH, info);
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writel(cmd, NAND_CMD);
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}
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int nfc_start_dma_and_wait_done(uint32_t n2m_cmd)
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{
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writel(n2m_cmd, NAND_CMD);
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writel(CE0 | IDLE, NAND_CMD);
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writel(CE0 | IDLE, NAND_CMD);
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return nfc_wait_command_fifo_done(NFC_DATA_FIFIO_TIMEOUT, 0);
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}
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void nfc_set_user_byte(u8 *oob_buf, uint64_t *info_buf, int ecc_steps)
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{
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uint64_t *info;
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int i, count;
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for (i = 0, count = 0; i < ecc_steps; i++, count += 2) {
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info = &info_buf[i];
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*info |= oob_buf[count];
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*info |= oob_buf[count + 1] << 8;
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}
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}
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void nfc_get_user_byte(u8 *oob_buf, uint64_t *info_buf, int ecc_steps)
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{
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uint64_t *info;
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int i, count;
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for (i = 0, count = 0; i < ecc_steps; i++, count += 2) {
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info = &info_buf[i];
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oob_buf[count] = *info;
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oob_buf[count + 1] = *info >> 8;
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}
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}
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int nfc_wait_data_and_ecc_engine_done(uint64_t *info_buf,
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unsigned char nsteps, int raw)
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{
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volatile uint64_t *info;
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int i, count = 0;
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if (nsteps < 1)
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return ERR_NFC_WRONG_PARAM;
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info = info_buf + nsteps - 1;
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while (count <= 10000) {
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invalidate_dcache_range((unsigned long)info_buf,
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(unsigned long)info_buf + sizeof(uint64_t) * 8);
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if (*info & ECC_COMPLETE)
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break;
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if (count == 10000) {
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writel(1 << 31, NAND_CMD);
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return ERR_DMA_TIMEOUT;
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}
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udelay(1);
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count++;
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}
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if (raw)
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return 0;
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for (i = 0, info = info_buf; i < nsteps; i++, info++) {
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if (ECC_ERR_CNT(*info) != ECC_UNCORRECTABLE)
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continue;
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if (ECC_ZERO_CNT(*info) < 0x0a)
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return 0;
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return ERROR_ECC;
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}
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return 0;
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}
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