60 lines
1.1 KiB
C
60 lines
1.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef PWM_MESON_H
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#define PWM_MESON_H
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#define NSEC_PER_SEC 1000000000ULL
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#define MESON_PWM0 0
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#define MESON_PWM1 1
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#define MESON_PWM2 2
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#define MESON_PWM3 3
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struct meson_pwm_reg {
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u32 dar;/* A/C/E Duty Register */
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u32 dbr;/* B/D/F Duty Register */
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u32 miscr;/* misc Register */
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u32 dsr;/*DS Register*/
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u32 tr;/*times Register*/
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u32 da2r;/* A2/C2/E2 Duty Register */
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u32 db2r;/* B2/D2/F2 Duty Register */
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u32 br;/*Blink Register*/
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};
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struct meson_pwm_data {
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u8 extern_clk; /* use external clktree */
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};
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enum pwm_polarity {
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PWM_POLARITY_NORMAL,
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PWM_POLARITY_INVERSED,
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};
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struct meson_pwm_state {
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unsigned int period;
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unsigned int duty_cycle;
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unsigned int hi;
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unsigned int lo;
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unsigned int pre_div;
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enum pwm_polarity polarity;
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bool enabled;
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};
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/*
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* Same as above but for u64 dividends. divisor must be a 32-bit
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* number.
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*/
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#define DIV_ROUND_CLOSEST_ULL(x, divisor)( \
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{ \
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typeof(divisor) __d = divisor; \
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unsigned long long _tmp = (x) + (__d) / 2; \
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do_div(_tmp, __d); \
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_tmp; \
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} \
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)
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#endif
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