488 lines
14 KiB
C
488 lines
14 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __HW_CTRL_H__
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#define __HW_CTRL_H__
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#include "amlnf_dev.h"
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#ifndef AML_NAND_UBOOT
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#include <linux/types.h>
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#endif /* AML_NAND_UBOOT */
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#define NF_REG_INDEX 0
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#define EXTCLK_REG_INDEX 1
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#define EXTPORT_REG_INDEX 2
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#define RETURN_PAGE_ALL_0XFF 0x01
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#define RETURN_PAGE_NEED_READRETRY 0x02
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#ifdef AML_NAND_UBOOT
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#define MESON_CPU_MAJOR_ID_M8 0x19
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#define MESON_CPU_MAJOR_ID_GX 0x21 //dbg code for gx pxp.
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#endif /* AML_NAND_UBOOT */
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#ifdef AML_NAND_UBOOT
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static inline int get_cpu_type(void)
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{
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return MESON_CPU_MAJOR_ID_GX;
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}
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#endif /* AML_NAND_UBOOT */
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#define NAND_CYCLE_DELAY ((get_cpu_type() >= MESON_CPU_MAJOR_ID_M8)?(84) : (90))
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#ifdef AML_NAND_UBOOT
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#define P_NAND_BASE (SD_EMMC_BASE_C | (1<<11))
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#define NAND_BASE_APB (P_NAND_BASE)
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#define NAND_CLK_CNTL (SD_EMMC_BASE_C) //fixme, need update the clock calculation.
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#endif /* AML_NAND_UBOOT */
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/* NAND Write Command And Read Status Register */
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#define P_NAND_CMD (0x00)
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/* NAND Configuration Register */
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#define P_NAND_CFG (0x04)
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/* NAND Data Address Register */
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#define P_NAND_DADR (0x08)
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/* NAND Information Address Register */
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#define P_NAND_IADR (0x0c)
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/* NAND Read Data Buffer Register */
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#define P_NAND_BUF (0x10)
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/* NAND Information Register */
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#define P_NAND_INFO (0x14)
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/* NAND DDR interface Register */
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#define P_NAND_DC (0x18)
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/* NAND DDR Address Register */
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#define P_NAND_ADR (0x1c)
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/* NAND DDR Low 32 bits Data Register */
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#define P_NAND_DL (0x20)
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/* NAND DDR High 32 bits Data Register */
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#define P_NAND_DH (0x24)
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/* NAND Command Queus Address Register */
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#define P_NAND_CADR (0x28)
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/* NAND Status Address Register */
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#define P_NAND_SADR (0x2c)
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/* NAND CS2: SDRAM/NAND pin sharing Register */
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#define P_NAND_PINS (0x30)
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/* NAND Version number Register */
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#define P_NAND_VER (0x38)
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/*...other way to access cfg...*/
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typedef union _nand_cfg {
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/** raw register data */
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u32 d;
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/** register bits */
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struct {
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u32 bus_cyc:5; //0
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u32 bus_tim:5; //5
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u32 sync:2; //10
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u32 cmd_start:1; //12
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u32 cmd_auto:1; //13
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u32 apb_mode:1; //14
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u32 spare_only:1; //15
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u32 sync_adj:1; //16
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u32 secure_des:1; //17
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u32 reserved18:2; //18
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u32 sts_irq_en:1; //20
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u32 cmd_irq_en:1; //21
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u32 reserved22:4; //25
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u32 oob_on:1; //26
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u32 oob_mode:1; //27
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u32 dc_ugt:1; //28
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u32 nand_wpn:1; //29
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u32 dma_power:1; //30
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u32 bus_power:1; //31
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} b;
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} nand_cfg_t;
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typedef struct _nand_reg {
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volatile u32 cmd;
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volatile u32 cfg;
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} nand_reg_t;
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extern nand_reg_t *p_nand_reg;
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static inline u32 amlnf_read_reg32(volatile uint32_t *_reg)
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{
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/*---*/
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#ifndef AML_NAND_UBOOT
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smp_rmb();
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#endif /* AML_NAND_UBOOT */
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return __raw_readl(_reg);
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};
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static inline void amlnf_write_reg32(volatile uint32_t *_reg,
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const u32 _value)
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{
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__raw_writel(_value, _reg);
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/*---*/
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#ifndef AML_NAND_UBOOT
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smp_mb();
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#endif /* AML_NAND_UBOOT */
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};
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static inline void amlnf_set_reg32_bits(volatile uint32_t *_reg,
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const u32 _value,
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const u32 _start,
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const u32 _len)
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{
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/*---*/
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#ifndef AML_NAND_UBOOT
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smp_rmb();
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#endif /* AML_NAND_UBOOT */
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__raw_writel(((__raw_readl(_reg) & ~(((1L << (_len))-1) << (_start)))
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| ((u32)((_value)&((1L<<(_len))-1)) << (_start))), _reg);
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/*---*/
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#ifndef AML_NAND_UBOOT
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smp_wmb();
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#endif /* AML_NAND_UBOOT */
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}
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static inline void amlnf_clrset_reg32_bits(volatile uint32_t *_reg,
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const u32 clr,
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const u32 set)
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{
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/*---*/
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#ifndef AML_NAND_UBOOT
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smp_rmb();
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#endif /* AML_NAND_UBOOT */
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__raw_writel((__raw_readl(_reg) & ~(clr)) | (set), _reg);
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/*---*/
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#ifndef AML_NAND_UBOOT
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smp_wmb();
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#endif /* AML_NAND_UBOOT */
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}
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static inline u32 amlnf_get_reg32_bits(volatile uint32_t *_reg,
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const u32 _start,
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const u32 _len)
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{
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/*---*/
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#ifndef AML_NAND_UBOOT
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smp_rmb();
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#endif /* AML_NAND_UBOOT */
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return (__raw_readl(_reg) >> (_start)) & ((1L << (_len)) - 1);
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}
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static inline void amlnf_set_reg32_mask(volatile uint32_t *_reg,
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const u32 _mask)
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{
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/*---*/
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#ifndef AML_NAND_UBOOT
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smp_rmb();
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#endif /* AML_NAND_UBOOT */
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__raw_writel((__raw_readl(_reg) | (_mask)), _reg);
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/*---*/
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#ifndef AML_NAND_UBOOT
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smp_wmb();
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#endif /* AML_NAND_UBOOT */
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}
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static inline void amlnf_clr_reg32_mask(volatile uint32_t *_reg,
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const u32 _mask)
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{
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/*---*/
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#ifndef AML_NAND_UBOOT
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smp_rmb();
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#endif /* AML_NAND_UBOOT */
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__raw_writel((__raw_readl(_reg) & (~(_mask))), _reg);
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/*---*/
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#ifndef AML_NAND_UBOOT
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smp_wmb();
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#endif /* AML_NAND_UBOOT */
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}
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/*
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#define nfc_readl(host, reg) \
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__raw_readl((host)->reg_base + P_##reg)
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#define nfc_writel(host, reg, value) \
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__raw_writel((value), (host)->reg_base + P_##reg)
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#define nfc_readw(host, reg) \
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__raw_readw((host)->reg_base + P_##reg)
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#define nfc_writew(host, reg, value) \
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__raw_writew((value), (host)->reg_base + P_##reg)
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#define nfc_readb(host, reg) \
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__raw_readb((host)->reg_base + P_##reg)
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#define nfc_writeb(host, reg, value) \
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__raw_writeb((value), (host)->reg_base + P_##reg)
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#define nfc_set_bits(host, reg) \
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{\
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u32 value;\
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value = __raw_readl((host)->reg_base + P_##reg);\
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value &= ~((( 1L << (_len) )-1) << (_start)); \
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value |= ((u32)((_value)&((1L<<(_len))-1)) << (_start));\
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__raw_writel(value, (host)->reg_base + P_##reg);\
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}
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*/
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//#define AMLNF_WRITE_REG(reg, val) (amlnf_write_reg32((volatile uint32_t *)(reg), (val)))
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#define AMLNF_WRITE_REG(reg, val) (amlnf_write_reg32(reg, (val)))
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//#define AMLNF_READ_REG(reg) (amlnf_read_reg32((volatile uint32_t *)(reg)))
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#define AMLNF_READ_REG(reg) (amlnf_read_reg32(reg))
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/*
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#define AMLNF_WRITE_REG_BITS(reg, val, start, len) \
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(amlnf_set_reg32_bits((volatile uint32_t *)(reg), (val), start, len))
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*/
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#define AMLNF_WRITE_REG_BITS(reg, val, start, len) \
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(amlnf_set_reg32_bits(reg, val, start, len))
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/*
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#define AMLNF_READ_REG_BITS(bus,reg, start, len) \
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(amlnf_get_reg32_bits(reg,start,len))
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*/
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/*
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#define AMLNF_CLEAR_REG_MASK(reg, mask) (amlnf_clr_reg32_mask((volatile uint32_t *)(reg), (mask)))
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#define AMLNF_SET_REG_MASK(reg, mask) (amlnf_set_reg32_mask((volatile uint32_t *)(reg), (mask)))
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*/
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#define AMLNF_CLEAR_REG_MASK(reg, mask) (amlnf_clr_reg32_mask(reg, mask))
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#define AMLNF_SET_REG_MASK(reg, mask) (amlnf_set_reg32_mask(reg, mask))
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/*
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#define NFC_SET_TIMING(host, mode, cycles, adjust) \
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AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, \
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((cycles)|((adjust&0xf)<<10)|((mode&7)<<5)), 0, 14)
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#define NFC_SET_CMD_START(host) \
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AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<12)
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#define NFC_SET_CMD_AUTO(host) \
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AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<13)
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#define NFC_SET_STS_IRQ(host, en) \
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AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, en, 20, 1)
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#define NFC_SET_CMD_IRQ(host, en) \
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AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, en, 21, 1)
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*/
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#define NFC_SET_TIMING_ASYC(host, bus_tim, bus_cyc) \
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AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, \
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((bus_cyc&31)|((bus_tim&31)<<5)|(0<<10)), \
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0, \
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12)
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/*
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#define NFC_SET_TIMING_SYNC(host, bus_tim, bus_cyc, sync_mode) \
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AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, \
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(bus_cyc&31)|((bus_tim&31)<<5)|((sync_mode&2)<<10), \
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0, \
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12)
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#define NFC_SET_TIMING_SYNC_ADJUST()
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#define NFC_SET_DMA_MODE(host, is_apb, spare_only) \
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AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, \
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((spare_only<<1)|(is_apb)), \
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14, \
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2)
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*/
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#define NFC_SET_OOB_MODE(host, mode) \
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AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, mode);
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#define NFC_CLR_OOB_MODE(host, mode) \
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AMLNF_CLEAR_REG_MASK((host)->reg_base + P_NAND_CFG, mode);
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/*
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#define NFC_ENABLE_STS_IRQ(host) \
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AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<20)
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#define NFC_DISABLE_STS_IRQ(host) \
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AMLNF_CLEAR_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<20)
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*/
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#define NFC_ENABLE_IO_IRQ(host) \
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AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<21)
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#define NFC_DISABLE_IO_IRQ(host) \
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AMLNF_CLEAR_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<21)
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#define NFC_ENABLE_ENCRYPT(host) \
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AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<17)
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#define NFC_DISABLE_ENCRYPT(host) \
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AMLNF_CLEAR_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<17)
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/**
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ADDR operations
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*/
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#define NFC_SET_DADDR(host, a) \
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(AMLNF_WRITE_REG((host)->reg_base + P_NAND_DADR, (u32)a))
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#define NFC_SET_IADDR(host, a) \
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(AMLNF_WRITE_REG((host)->reg_base + P_NAND_IADR, (u32)a))
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#define NFC_SET_SADDR(host, a) \
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(AMLNF_WRITE_REG((host)->reg_base + P_NAND_SADR, (u32)a))
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#define NFC_INFO_GET(host) \
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(AMLNF_READ_REG((host)->reg_base + P_NAND_CMD))
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#define NFC_GET_BUF(host) \
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AMLNF_READ_REG((host)->reg_base + P_NAND_BUF)
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#define NFC_SET_CFG(host, val) \
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(AMLNF_WRITE_REG((host)->reg_base + P_NAND_CFG, (u32)val))
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/*
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Common Nand Read Flow
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*/
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#define CE0 (0xe<<10)
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#define CE1 (0xd<<10)
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#define CE2 (0xb<<10)
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#define CE3 (0x7<<10)
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#define CE_NOT_SEL (0xf<<10)
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#define IO4 ((0xe<<10)|(1<<18))
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#define IO5 ((0xd<<10)|(1<<18))
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#define IO6 ((0xb<<10)|(1<<18))
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#define CLE (0x5<<14)
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#define ALE (0x6<<14)
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#define DWR (0x4<<14)
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#define DRD (0x8<<14)
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#define IDLE (0xc<<14)
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#define RB (1<<20)
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#define STANDBY (0xf<<10)
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#define M2N ((0<<17) | (2<<20) | (1<<19))
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#define N2M ((1<<17) | (2<<20) | (1<<19))
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#define M2N_NORAN 0x00200000
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#define N2M_NORAN 0x00220000
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#define STS ((3<<17) | (2<<20))
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#define ADL ((0<<16) | (3<<20))
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#define ADH ((1<<16) | (3<<20))
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#define AIL ((2<<16) | (3<<20))
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#define AIH ((3<<16) | (3<<20))
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#define ASL ((4<<16) | (3<<20))
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#define ASH ((5<<16) | (3<<20))
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#define SEED ((8<<16) | (3<<20))
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#define SEED_OFFSET 0xc2
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/**
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Nand Flash Controller (M1)
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Global Macros
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*/
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/**
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Config Group
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*/
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/**
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CMD relative Macros
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Shortage word . NFCC
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*/
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#define NFC_CMD_IDLE(ce, time) ((ce)|IDLE|(time&0x3ff))
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#define NFC_CMD_CLE(ce, cmd) ((ce)|CLE | (cmd & 0x0ff))
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#define NFC_CMD_ALE(ce, addr) ((ce)|ALE | (addr&0x0ff))
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#define NFC_CMD_STANDBY(time) (STANDBY | (time&0x3ff))
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#define NFC_CMD_ADL(addr) (ADL | (addr&0xffff))
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#define NFC_CMD_ADH(addr) (ADH|((addr>>16)&0xffff))
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#define NFC_CMD_AIL(addr) (AIL | (addr&0xffff))
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#define NFC_CMD_AIH(addr) (AIH|((addr>>16)&0xffff))
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#define NFC_CMD_DWR(ce, data) (ce|DWR | (data&0xff))
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#define NFC_CMD_DRD(ce, size) (ce|DRD|size)
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#define NFC_CMD_RB(ce, time) ((ce)|RB | (time&0x1f))
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#define NFC_CMD_RB_INT(ce, time) \
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((ce)|RB|(((ce>>10)^0xf)<<14)|(time&0x1f))
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#define NFC_CMD_RBIO(time, io) (RB|io|(time&0x1f))
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#define NFC_CMD_RBIO_IRQ(time) (RB|IO6|(1<<16)|(time&0x1f))
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#define NFC_CMD_RBIO_INT(io, time) (RB|(((io>>10)^0x7)<<14)|(time&0x1f))
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#define NFC_CMD_SEED(seed) (SEED|(SEED_OFFSET + (seed&0x7fff)))
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#define NFC_CMD_STS(tim) (STS|(tim&3))
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#define NFC_CMD_M2N(ran, ecc, sho, pgsz, pag) \
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((ran?M2N:M2N_NORAN)|(ecc<<14)|(sho<<13)|((pgsz&0x7f)<<6)|(pag&0x3f))
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#define NFC_CMD_N2M(ran, ecc, sho, pgsz, pag)\
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((ran?N2M:N2M_NORAN)|(ecc<<14)|(sho<<13)|((pgsz&0x7f)<<6)|(pag&0x3f))
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/**
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Alias for CMD
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#define NFC_CMD_D_ADR(addr) NFC_CMD_ADL(addr), NFC_CMD_ADH(addr)
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#define NFC_CMD_I_ADR(addr) NFC_CMD_ADI(addr), NFC_CMD_ADI(addr)
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*/
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#define NAND_ECC_NONE (0x0)
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#define NAND_ECC_BCH8 (0x1)
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#define NAND_ECC_BCH8_1K (0x2)
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#define NAND_ECC_BCH16_1K (0x3)
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#define NAND_ECC_BCH24_1K (0x4)
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#define NAND_ECC_BCH24_1K_M8 (0x3)
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#define NAND_ECC_BCH30_1K (0x5)
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#define NAND_ECC_BCH30_1K_M8 (0x4)
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#define NAND_ECC_BCH40_1K (0x6)
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#define NAND_ECC_BCH40_1K_M8 (0x5)
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#define NAND_ECC_BCH50_1K_M8 (0x6)
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#define NAND_ECC_BCH60_1K (0x7)
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#define NAND_ECC_BCH_SHORT (0x8)
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/**
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Register Operation and Controller Status
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*/
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#define NFC_SEND_CMD(host, cmd) \
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(AMLNF_WRITE_REG((host)->reg_base + P_NAND_CMD, cmd))
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#define NFC_READ_INFO(host) \
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(AMLNF_READ_REG((host)->reg_base + P_NAND_CMD))
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/**
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Send command directly
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*/
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#define NFC_SEND_CMD_IDLE(host, time) \
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{\
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while (NFC_CMDFIFO_SIZE(host) > 0)\
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; \
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NFC_SEND_CMD(host, NFC_CMD_IDLE((host)->chip_selected, time)); \
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}
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#define NFC_SEND_CMD_CLE(host, ce, cmd) \
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NFC_SEND_CMD(host, NFC_CMD_CLE(ce, cmd))
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#define NFC_SEND_CMD_ALE(host, ce, addr) \
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NFC_SEND_CMD(host, NFC_CMD_ALE(ce, addr))
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#define NFC_SEND_CMD_STANDBY(host, time) \
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NFC_SEND_CMD(host, NFC_CMD_STANDBY(time))
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#define NFC_SEND_CMD_ADL(host, addr) \
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NFC_SEND_CMD(host, NFC_CMD_ADL(addr))
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#define NFC_SEND_CMD_ADH(host, addr) \
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NFC_SEND_CMD(host, NFC_CMD_ADH(addr))
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#define NFC_SEND_CMD_AIL(host, addr) \
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NFC_SEND_CMD(host, NFC_CMD_AIL(addr))
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#define NFC_SEND_CMD_AIH(host, addr) \
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NFC_SEND_CMD(host, NFC_CMD_AIH(addr))
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|
#define NFC_SEND_CMD_DWR(host, ce, data) \
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NFC_SEND_CMD(host, NFC_CMD_DWR(ce, data))
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|
#define NFC_SEND_CMD_DRD(host, ce, size) \
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|
NFC_SEND_CMD(host, NFC_CMD_DRD(ce, size))
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|
#define NFC_SEND_CMD_RB(host, ce, time) \
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NFC_SEND_CMD(host, NFC_CMD_RB(ce, time))
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|
#define NFC_SEND_CMD_SEED(host, seed) \
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|
NFC_SEND_CMD(host, NFC_CMD_SEED(seed))
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|
#define NFC_SEND_CMD_M2N(host, ran, ecc, sho, pgsz, pag) \
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|
NFC_SEND_CMD(host, NFC_CMD_M2N(ran, ecc, sho, pgsz, pag))
|
|
#define NFC_SEND_CMD_N2M(host, ran, ecc, sho, pgsz, pag) \
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|
NFC_SEND_CMD(host, NFC_CMD_N2M(ran, ecc, sho, pgsz, pag))
|
|
|
|
#define NFC_SEND_CMD_M2N_RAW(host, ran, len) \
|
|
NFC_SEND_CMD(host, (ran?M2N:M2N_NORAN)|(len&0x3fff))
|
|
#define NFC_SEND_CMD_N2M_RAW(host, ran, len) \
|
|
NFC_SEND_CMD(host, (ran?N2M:N2M_NORAN)|(len&0x3fff))
|
|
|
|
#define NFC_SEND_CMD_STS(host, time, irq) \
|
|
NFC_SEND_CMD(host, NFC_CMD_STS(time | irq))
|
|
|
|
#define NFC_SEND_CMD_RB_IRQ(host, time) \
|
|
NFC_SEND_CMD(host, NFC_CMD_RBIO_IRQ(time))
|
|
|
|
/**
|
|
Cmd Info Macros
|
|
*/
|
|
#define NFC_CMDFIFO_SIZE(host) ((NFC_INFO_GET(host)>>22)&0x1f)
|
|
#define NFC_CHECEK_RB_TIMEOUT(host) ((NFC_INFO_GET(host)>>27)&0x1)
|
|
#define NFC_FIFO_CUR_CMD(host) ((NFC_INFO_GET(host)>>22)&0x3FFFFF)
|
|
#define NFC_GET_RB_STATUS(host, ce) \
|
|
(((NFC_INFO_GET(host)>>28)&(~(ce>>10)))&0xf)
|
|
|
|
|
|
#define NAND_INFO_DONE(a) (((a)>>31)&1)
|
|
#define NAND_ECC_ENABLE(a) (((a)>>30)&1)
|
|
#define NAND_ECC_CNT(a) (((a)>>24)&0x3f)
|
|
#define NAND_ZERO_CNT(a) (((a)>>16)&0x3f)
|
|
#define NAND_INFO_DATA_2INFO(a) ((a)&0xffff)
|
|
#define NAND_INFO_DATA_1INFO(a) ((a)&0xff)
|
|
|
|
#define POR_CONFIG READ_CBUS_REG(ASSIST_POR_CONFIG)
|
|
|
|
#define POC_NAND_CFG (1<<2)
|
|
#define POC_NAND_NO_RB (1<<0)
|
|
#define POC_NAND_ASYNC (1<<7)
|
|
|
|
#endif /* __HW_CTRL_H__ */
|
|
|