79 lines
1.6 KiB
C
79 lines
1.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef AMLNAND_PHYDEV_H_INCLUDED
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#define AMLNAND_PHYDEV_H_INCLUDED
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#include "amlnf_dev.h"
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/***nand CE/RB pinmux setting***/
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#define AML_NAND_CE0 0xe
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#define AML_NAND_CE1 0xd
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#define AML_NAND_CE2 0xb
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#define AML_NAND_CE3 0x7
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#define CE_PAD_DEFAULT \
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((AML_NAND_CE0) | \
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(AML_NAND_CE1 << 4) | \
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(AML_NAND_CE2 << 8) | \
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(AML_NAND_CE3 << 12))
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/*
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#define RB_PAD_DEFAULT ((AML_NAND_CE0) | (AML_NAND_CE1 << 4))
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*/
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#define RB_PAD_DEFAULT (AML_NAND_CE0)
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#define MAX_CHIP_NUM 4
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#define PER_INFO_BYTE 8
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/***nand device option***/
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#define DEV_SLC_MODE (1<<0)
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#define DEV_SERIAL_CHIP_MODE (0<<1)
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#define DEV_MULTI_CHIP_MODE (1<<1)
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#define DEV_MULTI_PLANE_MODE (1<<2)
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#define DEV_SINGLE_PLANE_MODE (0<<2)
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#define DEV_USE_SHAREPAGE_MODE (1<<4)
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#define DEV_ECC_SOFT_MODE (1<<3)
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#define DEV_ECC_HW_MODE (0<<3)
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#define NAND_SHUT_DOWN (1 << 16)
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#define NAND_CODE_OPTION (DEV_MULTI_PLANE_MODE | DEV_MULTI_CHIP_MODE | DEV_USE_SHAREPAGE_MODE)
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#define NAND_DATA_OPTION (DEV_MULTI_PLANE_MODE | DEV_MULTI_CHIP_MODE | DEV_USE_SHAREPAGE_MODE)
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/*
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* Status for nand chip
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*/
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enum chip_state_t {
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CHIP_READY,
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CHIP_STATUS,
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CHIP_ERASING,
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CHIP_ERASE_SUSPENDING,
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CHIP_ERASE_SUSPENDED,
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CHIP_WRITING,
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CHIP_WRITE_SUSPENDING,
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CHIP_WRITE_SUSPENDED,
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CHIP_PM_SUSPENDED,
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CHIP_SYNCING,
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CHIP_UNLOADING,
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CHIP_LOCKING,
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CHIP_UNLOCKING,
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CHIP_POINT,
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CHIP_SHUTDOWN,
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CHIP_READING,
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CHIP_RESETING,
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CHIP_PREPARING_ERASE,
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CHIP_VERIFYING_ERASE,
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CHIP_UNKNOWN
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};
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extern int amlphy_prepare(u32 flag);
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#endif
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