58 lines
1.4 KiB
C
58 lines
1.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __AML_NF_CFG_H__
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#define __AML_NF_CFG_H__
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/*************stage***************/
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#define AML_NAND_UBOOT //For uboot
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#define EXPORT_SYMBOL(...)
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/**************PHY****************/
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#define AML_SLC_NAND_SUPPORT
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#define AML_MLC_NAND_SUPPORT
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#define __DEBUG_L04__ (1)
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#define AML_NAND_DBG (0)
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#define AML_CFG_INSIDE_PARTTBL (0)
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#define AML_CFG_2PLANE_READ_EN (1)
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/* support nand with readretry&e-slc */
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#define AML_CFG_NEW_NAND_SUPPORT (1)
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/* new oob mode */
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#define AML_CFG_NEWOOB_EN (1)
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/* store dtd in rsv area! */
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#define AML_CFG_DTB_RSV_EN (1)
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/* store key in rsv area */
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#define AML_CFG_KEY_RSV_EN (1)
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#define NAND_ADJUST_PART_TABLE
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#ifdef NAND_ADJUST_PART_TABLE
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#define ADJUST_BLOCK_NUM 4
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#else
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#define ADJUST_BLOCK_NUM 0
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#endif
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/* ASYNC = 0x0 NVDDR_1= 0x10 NVDDR_2 = 0x20 */
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#define NAND_OPMODE_ASYNC 0x0
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#define NAND_OPMODE_NVDDR1 0x10
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#define NAND_OPMODE_NVDDR2 0x20
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#if 1
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#define NAND_ONFI_MODE_OP (NAND_OPMODE_ASYNC)
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#else
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#define NAND_ONFI_MODE_OP (NAND_OPMODE_NVDDR1)
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#endif
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/*do not use rb irq under uboot*/
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/* #define AML_NAND_RB_IRQ */
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/*
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#define AML_NAND_DMA_POLLING
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*/
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extern int is_phydev_off_adjust(void);
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extern int get_adjust_block_num(void);
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#endif //__AML_NF_CFG_H__
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