446 lines
11 KiB
C
446 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2017 - Beniamino Galvani <[email protected]>
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*/
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#include <common.h>
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#include <asm/arch-meson/i2c.h>
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <i2c.h>
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#define I2C_TIMEOUT_MS 100
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/* Control register fields */
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#define REG_CTRL_START BIT(0)
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#define REG_CTRL_ACK_IGNORE BIT(1)
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#define REG_CTRL_STATUS BIT(2)
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#define REG_CTRL_ERROR BIT(3)
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#define REG_CTRL_CLKDIV_SHIFT 12
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#define REG_CTRL_CLKDIV_MASK GENMASK(21, 12)
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#define REG_CTRL_CLKDIVEXT_SHIFT 28
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#define REG_CTRL_CLKDIVEXT_MASK GENMASK(29, 28)
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enum {
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TOKEN_END = 0,
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TOKEN_START,
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TOKEN_SLAVE_ADDR_WRITE,
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TOKEN_SLAVE_ADDR_READ,
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TOKEN_DATA,
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TOKEN_DATA_LAST,
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TOKEN_STOP,
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};
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struct i2c_regs {
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u32 ctrl;
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u32 slave_addr;
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u32 tok_list0;
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u32 tok_list1;
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u32 tok_wdata0;
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u32 tok_wdata1;
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u32 tok_rdata0;
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u32 tok_rdata1;
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};
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struct meson_i2c_data {
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u8 delay_adjust;
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u8 div_factor;
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u32 clkin_rate;
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};
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struct meson_i2c {
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struct clk clk;
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struct i2c_regs *regs;
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struct i2c_msg *msg; /* Current I2C message */
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bool last; /* Whether the message is the last */
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uint count; /* Number of bytes in the current transfer */
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uint pos; /* Position of current transfer in message */
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u32 tokens[2]; /* Sequence of tokens to be written */
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uint num_tokens; /* Number of tokens to be written */
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struct meson_i2c_data *data;
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};
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static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
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{
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i2c->tokens[0] = 0;
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i2c->tokens[1] = 0;
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i2c->num_tokens = 0;
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}
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static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
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{
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if (i2c->num_tokens < 8)
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i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4);
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else
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i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4);
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i2c->num_tokens++;
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}
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/*
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* Retrieve data for the current transfer (which can be at most 8
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* bytes) from the device internal buffer.
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*/
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static void meson_i2c_get_data(struct meson_i2c *i2c, u8 *buf, int len)
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{
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u32 rdata0, rdata1;
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int i;
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rdata0 = readl(&i2c->regs->tok_rdata0);
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rdata1 = readl(&i2c->regs->tok_rdata1);
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debug("meson i2c: read data %08x %08x len %d\n", rdata0, rdata1, len);
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for (i = 0; i < min(4, len); i++)
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*buf++ = (rdata0 >> i * 8) & 0xff;
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for (i = 4; i < min(8, len); i++)
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*buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
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}
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/*
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* Write data for the current transfer (which can be at most 8 bytes)
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* to the device internal buffer.
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*/
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static void meson_i2c_put_data(struct meson_i2c *i2c, u8 *buf, int len)
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{
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u32 wdata0 = 0, wdata1 = 0;
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int i;
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for (i = 0; i < min(4, len); i++)
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wdata0 |= *buf++ << (i * 8);
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for (i = 4; i < min(8, len); i++)
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wdata1 |= *buf++ << ((i - 4) * 8);
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writel(wdata0, &i2c->regs->tok_wdata0);
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writel(wdata1, &i2c->regs->tok_wdata1);
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debug("meson i2c: write data %08x %08x len %d\n", wdata0, wdata1, len);
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}
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/*
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* Prepare the next transfer: pick the next 8 bytes in the remaining
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* part of message and write tokens and data (if needed) to the
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* device.
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*/
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static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
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{
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bool write = !(i2c->msg->flags & I2C_M_RD);
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int i;
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i2c->count = min(i2c->msg->len - i2c->pos, 8u);
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for (i = 0; i + 1 < i2c->count; i++)
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meson_i2c_add_token(i2c, TOKEN_DATA);
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if (i2c->count) {
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if (write || i2c->pos + i2c->count < i2c->msg->len)
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meson_i2c_add_token(i2c, TOKEN_DATA);
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else
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meson_i2c_add_token(i2c, TOKEN_DATA_LAST);
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}
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if (write)
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meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
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if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len)
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meson_i2c_add_token(i2c, TOKEN_STOP);
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writel(i2c->tokens[0], &i2c->regs->tok_list0);
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writel(i2c->tokens[1], &i2c->regs->tok_list1);
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}
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static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
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{
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int token;
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token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ :
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TOKEN_SLAVE_ADDR_WRITE;
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clrsetbits_le32(&i2c->regs->slave_addr, GENMASK(7, 0),
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(msg->addr << 1) & GENMASK(7, 0));
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meson_i2c_add_token(i2c, TOKEN_START);
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meson_i2c_add_token(i2c, token);
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}
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static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg,
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int last)
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{
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ulong start;
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debug("meson i2c: %s addr 0x%x len %u\n",
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(msg->flags & I2C_M_RD) ? "read" : "write",
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msg->addr, msg->len);
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i2c->msg = msg;
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i2c->last = last;
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i2c->pos = 0;
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i2c->count = 0;
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meson_i2c_reset_tokens(i2c);
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meson_i2c_do_start(i2c, msg);
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do {
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meson_i2c_prepare_xfer(i2c);
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/* start the transfer */
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setbits_le32(&i2c->regs->ctrl, REG_CTRL_START);
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start = get_timer(0);
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while (readl(&i2c->regs->ctrl) & REG_CTRL_STATUS) {
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if (get_timer(start) > I2C_TIMEOUT_MS) {
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clrbits_le32(&i2c->regs->ctrl, REG_CTRL_START);
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debug("meson i2c: timeout\n");
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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meson_i2c_reset_tokens(i2c);
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clrbits_le32(&i2c->regs->ctrl, REG_CTRL_START);
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if (readl(&i2c->regs->ctrl) & REG_CTRL_ERROR) {
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debug("meson i2c: error\n");
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return -EREMOTEIO;
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}
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if ((msg->flags & I2C_M_RD) && i2c->count) {
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meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos,
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i2c->count);
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}
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i2c->pos += i2c->count;
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} while (i2c->pos < msg->len);
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return 0;
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}
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static int meson_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
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int nmsgs)
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{
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struct meson_i2c *i2c = dev_get_priv(bus);
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int i, ret = 0;
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#ifdef CONFIG_ARMV8_MULTIENTRY
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if (in_smp())
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spin_lock(&bus->lock);
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#endif
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for (i = 0; i < nmsgs; i++) {
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ret = meson_i2c_xfer_msg(i2c, msg + i, i == nmsgs - 1);
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if (ret) {
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#ifdef CONFIG_ARMV8_MULTIENTRY
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if (in_smp())
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spin_unlock(&bus->lock);
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#endif
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return ret;
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}
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}
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#ifdef CONFIG_ARMV8_MULTIENTRY
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if (in_smp())
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spin_unlock(&bus->lock);
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#endif
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return 0;
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}
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/*
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* Count = clk/freq = H + L
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* Duty = H/(H + L) = 1/2 -- duty 50%
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* 1. register description
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* in I2C_CONTROL_REG , n = [28:29][21:12], control the high level time
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* n consists of 12bit, [21:12] is the low 10bit,
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* [28:29] is the bit 11 and 12.
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* in I2C_SLAVE_ADDRESS, m = [27:16], control the low level time,
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* bit 28 enable the function
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*
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* 2.I2C controller internal characteristic
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* H = n + delay
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* L = 2m
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* (H:high clock counts equals n + 15 clocks which
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* cost by sampling and filtering
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* L:low clock counts equals m multiply by 2)
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*
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* 3.high level and low level relationship:
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* H/L = (n + 15)/2m = 1/1
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* H+L = 2m + n +15 = count
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* Count = 166M/freq = 166M/100k
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*
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* =>
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*
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* n = Count/2 - delay
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* m = Count/4
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*
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* n equals div_h, m equals div_l below
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* Standard Mode : 100k
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*/
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static int meson_i2c_set_std_speed(struct udevice *bus, unsigned int speed)
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{
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struct meson_i2c *i2c = dev_get_priv(bus);
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unsigned int clk_rate = MESON_I2C_CLK_RATE;
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unsigned int div_h, div_l;
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unsigned int div_temp;
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div_temp = DIV_ROUND_UP(clk_rate, speed);
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div_h = DIV_ROUND_UP(div_temp, 2) - i2c->data->delay_adjust;
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div_l = DIV_ROUND_UP(div_temp, 4);
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/* clock divider has 12 bits */
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if (div_h >= (1 << 12)) {
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debug("requested bus frequency too low\n");
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div_h = (1 << 12) - 1;
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}
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if (div_l >= (1 << 12)) {
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debug("requested bus frequency too low\n");
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div_l = (1 << 12) - 1;
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}
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/*control reg:12-21 bits*/
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clrsetbits_le32(&i2c->regs->ctrl, REG_CTRL_CLKDIV_MASK,
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(div_h & GENMASK(9, 0)) << REG_CTRL_CLKDIV_SHIFT);
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clrsetbits_le32(&i2c->regs->ctrl, REG_CTRL_CLKDIVEXT_MASK,
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(div_h >> 10) << REG_CTRL_CLKDIVEXT_SHIFT);
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/* set SCL low delay */
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clrsetbits_le32(&i2c->regs->slave_addr, GENMASK(27, 16),
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(div_l << 16) & GENMASK(27, 16));
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/* enable to control SCL low time */
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clrsetbits_le32(&i2c->regs->slave_addr, BIT(28), BIT(28));
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debug("meson i2c: set clk %u, src %u, div_h %u, div_l %u\n",
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speed, clk_rate, div_h, div_l);
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return 0;
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}
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/*
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* Duty = H/(H + L) = 2/5 -- duty 40%% H/L = 2/3
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* Refer to meson_i2c_set_std_speed note.
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* Fast Mode : 400k
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* High Mode : 3400k
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*/
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static int meson_i2c_set_fast_speed(struct udevice *bus, unsigned int speed)
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{
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struct meson_i2c *i2c = dev_get_priv(bus);
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unsigned int clk_rate = MESON_I2C_CLK_RATE;
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unsigned int div_h, div_l;
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unsigned int div_temp;
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div_temp = DIV_ROUND_UP(clk_rate * 2, speed * 5);
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div_h = div_temp - i2c->data->delay_adjust;
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div_l = DIV_ROUND_UP(clk_rate * 3, speed * 10);
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/* clock divider has 12 bits */
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if (div_h >= (1 << 12)) {
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debug("requested bus frequency too low\n");
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div_h = (1 << 12) - 1;
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}
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if (div_l >= (1 << 12)) {
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debug("requested bus frequency too low\n");
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div_l = (1 << 12) - 1;
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}
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/*control reg:12-21 bits*/
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clrsetbits_le32(&i2c->regs->ctrl, REG_CTRL_CLKDIV_MASK,
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(div_h & GENMASK(9, 0)) << REG_CTRL_CLKDIV_SHIFT);
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clrsetbits_le32(&i2c->regs->ctrl, REG_CTRL_CLKDIVEXT_MASK,
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(div_h >> 10) << REG_CTRL_CLKDIVEXT_SHIFT);
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/* set SCL low delay */
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clrsetbits_le32(&i2c->regs->slave_addr, GENMASK(27, 16),
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(div_l << 16) & GENMASK(27, 16));
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/* enable to control SCL low time */
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clrsetbits_le32(&i2c->regs->slave_addr, BIT(28), BIT(28));
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debug("meson i2c: set clk %u, src %u, div_h %u, div_l %u\n",
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speed, clk_rate, div_h, div_l);
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return 0;
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}
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static int meson_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
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{
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#ifdef CONFIG_ARMV8_MULTIENTRY
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if (in_smp())
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spin_lock(&bus->lock);
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#endif
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if (speed >= 400000)
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meson_i2c_set_fast_speed(bus, speed);
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else
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meson_i2c_set_std_speed(bus, speed);
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#ifdef CONFIG_ARMV8_MULTIENTRY
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if (in_smp())
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spin_unlock(&bus->lock);
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#endif
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return 0;
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}
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static int meson_i2c_probe(struct udevice *bus)
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{
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struct meson_i2c *i2c = dev_get_priv(bus);
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i2c->data = (struct meson_i2c_data *)dev_get_driver_data(bus);
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clrbits_le32(&i2c->regs->ctrl, REG_CTRL_START);
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#ifdef CONFIG_ARMV8_MULTIENTRY
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spin_lock_init(&bus->lock);
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#endif
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return 0;
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}
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static int meson_i2c_ofdata_to_platdata(struct udevice *dev)
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{
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struct meson_i2c *i2c = dev_get_priv(dev);
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i2c->regs = dev_read_addr_ptr(dev);
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return 0;
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}
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static const struct meson_i2c_data i2c_meson_meson6_data = {
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.div_factor = 4,
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.delay_adjust = 15,
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.clkin_rate = MESON_I2C_CLK_RATE,
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};
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static const struct meson_i2c_data i2c_meson_gx_data = {
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.div_factor = 4,
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.delay_adjust = 15,
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.clkin_rate = MESON_I2C_CLK_RATE,
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};
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static const struct meson_i2c_data i2c_meson_data = {
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.div_factor = 3,
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.delay_adjust = 15,
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.clkin_rate = MESON_I2C_CLK_RATE,
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};
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static const struct meson_i2c_data i2c_meson_a1_data = {
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.div_factor = 3,
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.delay_adjust = 15,
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.clkin_rate = 64000000,
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};
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static const struct dm_i2c_ops meson_i2c_ops = {
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.xfer = meson_i2c_xfer,
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.set_bus_speed = meson_i2c_set_bus_speed,
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};
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static const struct udevice_id meson_i2c_ids[] = {
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{ .compatible = "amlogic,meson6-i2c", .data = (long)&i2c_meson_meson6_data },
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{ .compatible = "amlogic,meson-gx-i2c", .data = (long)&i2c_meson_gx_data },
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{ .compatible = "amlogic,meson-gxbb-i2c", .data = (long)&i2c_meson_gx_data },
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{ .compatible = "amlogic,meson-i2c", .data = (long)&i2c_meson_data },
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{ .compatible = "amlogic,meson-a1-i2c", .data = (long)&i2c_meson_a1_data },
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{ }
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};
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U_BOOT_DRIVER(i2c_meson) = {
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.name = "i2c_meson",
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.id = UCLASS_I2C,
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.of_match = meson_i2c_ids,
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.ofdata_to_platdata = meson_i2c_ofdata_to_platdata,
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.probe = meson_i2c_probe,
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.priv_auto_alloc_size = sizeof(struct meson_i2c),
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.ops = &meson_i2c_ops,
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};
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