363 lines
9.7 KiB
C
363 lines
9.7 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <bitfield.h>
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#include <dm.h>
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#include <errno.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <power/regulator.h>
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#include <clk.h>
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#include <asm/arch/usb.h>
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#include <amlogic/cpu_id.h>
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#include <linux/compat.h>
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#include <linux/ioport.h>
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#include <asm-generic/gpio.h>
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#define PHY20_RESET_LEVEL_BIT 8
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#define PHY21_RESET_LEVEL_BIT 9
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#define PHY22_RESET_LEVEL_BIT 7
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#define USB_RESET_BIT 4
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#define USB_2_DRD_BIT 10
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#define USB2H_BIT 11
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#define USB2_PHY_PLL_OFFSET_40 (0x09400414)
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#define USB2_PHY_PLL_OFFSET_44 (0x927E0000)
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#define USB2_PHY_PLL_OFFSET_48 (0xac5f69e5)
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#define USB2_PHY_PLL_OFFSET_10 (0x80000fff)
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#define USB2_PHY_PLL_OFFSET_34 (0x78000)
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#define USB2_REVB_PHY_PLL_OFFSET_34 (0x70000)
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#define USB2_PHY_PLL_OFFSET_38_CLEAR (0)
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#define USB2_PHY_PLL_OFFSET_38_SET (0xe0004)
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#define USB2_PHY_PLL_OFFSET_50 (0xfe18)
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#define USB2_PHY_PLL_OFFSET_54 (0x2a)
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#define TUNING_DISCONNECT_THRESHOLD 0x3C
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#define DISCONNECT_THRESHOLD_ENHANCE 0x2
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#define PHY_20_BASE 0xfe03c000
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#define PHY_COMP_BASE 0xfe03a000
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#define RESET_BASE 0xFE002000
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#define RESET_LEVEL_BASE 0xFE002040
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#define AMLOGIC_CTR_COUNT (0x2)
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struct ctr_info {
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struct phy usb_phys[4];
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unsigned long phy_count;
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};
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static struct ctr_info ctr[AMLOGIC_CTR_COUNT];
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//static struct phy usb_phys[4];
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int get_usbphy_baseinfo(void)
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{
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struct udevice *bus;
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struct uclass *uc;
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int ret, i, j = 0;
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int count;
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for (i = 0; i < AMLOGIC_CTR_COUNT; i++) {
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if (ctr[i].usb_phys[0].dev && ctr[i].usb_phys[1].dev)
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return 0;
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}
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ret = uclass_get(UCLASS_USB, &uc);
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if (ret)
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return ret;
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uclass_foreach_dev(bus, uc) {
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debug("bus->name=%s, bus->driver->name =%s\n",
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bus->name, bus->driver->name);
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count = dev_count_phandle_with_args(bus, "phys", "#phy-cells");
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debug("usb phy count=%u\n", count);
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if (count <= 0)
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return count;
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if (j >= AMLOGIC_CTR_COUNT) {
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pr_err("AMLOGIC_CTR_COUNT is small: %d\n", j);
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return -1;
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}
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for (i = 0; i < count; i++) {
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ret = generic_phy_get_by_index(bus, i, &ctr[j].usb_phys[i]);
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if (ret && ret != -ENOENT) {
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pr_err("Failed to get USB PHY%d for %s\n",
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i, bus->name);
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return ret;
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}
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ret = generic_phy_getinfo(&ctr[j].usb_phys[i]);
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if (ret)
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return ret;
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}
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ctr[j].phy_count = count;
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j++;
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}
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return 0;
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}
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void usb_aml_detect_operation(int argc, char * const argv[])
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{
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struct phy_aml_usb2_priv *usb2_priv;
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struct phy_aml_usb3_priv *usb3_priv;
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int ret, i;
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ret = get_usbphy_baseinfo();
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if (ret) {
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printf("get usb dts failed\n");
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return;
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}
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for (i = 0; i < AMLOGIC_CTR_COUNT; i++) {
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usb2_priv = dev_get_priv(ctr[i].usb_phys[0].dev);
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usb3_priv = dev_get_priv(ctr[i].usb_phys[1].dev);
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if (usb3_priv) {
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printf("priv->usb3 port num = %d, config addr=0x%08x\n",
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usb3_priv->usb3_port_num, usb3_priv->base_addr);
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}
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if (usb2_priv) {
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printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n",
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usb2_priv->base_addr, usb2_priv->reset_addr);
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printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n",
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usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0],
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usb2_priv->usb_phy2_pll_base_addr[1]);
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printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr);
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}
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}
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}
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static void usb_set_calibration_trim(uint32_t volatile *phy2_pll_base)
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{
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uint32_t cali, value, i;
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uint8_t cali_en;
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cali = readl(SYSCTRL_SEC_STATUS_REG12);
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//printf("SYSCTRL_SEC_STATUS_REG12=0x%08x\n", cali);
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/*****if cali_en ==0, set 0x10 to the default value: 0x1700****/
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cali_en = (cali >> 12) & 0x1;
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cali = cali >> 8;
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if (cali_en) {
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cali = cali & 0xf;
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if (cali > 12)
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cali = 12;
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} else {
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cali = 0x7;
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}
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value = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10));
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value &= (~0xfff);
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for (i = 0; i < cali; i++)
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value |= (1 << i);
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(*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)) =
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value;
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printf("0x10 trim value=0x%08x\n", value);
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}
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void usb_reset(unsigned int reset_addr, int bit)
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{
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*(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit);
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}
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static void usb_enable_phy_pll(u32 base_addr)
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{
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*(uint32_t *)(unsigned long)
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RESET_LEVEL_BASE |= (1 << PHY20_RESET_LEVEL_BIT);
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*(uint32_t *)(unsigned long)
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RESET_LEVEL_BASE |= (1 << PHY21_RESET_LEVEL_BIT);
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*(uint32_t *)(unsigned long)
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RESET_LEVEL_BASE |= (1 << PHY22_RESET_LEVEL_BIT);
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}
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void set_usb_pll(uint32_t phy2_pll_base)
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{
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int val;
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(*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40)) =
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(USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE);
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(*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) =
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USB2_PHY_PLL_OFFSET_44;
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(*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) =
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USB2_PHY_PLL_OFFSET_48;
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udelay(100);
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(*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40)) =
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(((USB2_PHY_PLL_OFFSET_40) | (USB_PHY2_ENABLE)) & (~(USB_PHY2_RESET)));
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(*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50)) =
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USB2_PHY_PLL_OFFSET_50;
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(*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54)) =
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USB2_PHY_PLL_OFFSET_54;
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usb_set_calibration_trim((uint32_t volatile *)(u64)phy2_pll_base);
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(*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) =
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TUNING_DISCONNECT_THRESHOLD;
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val = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x38));
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val &= ~0xc000000;
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val |= (DISCONNECT_THRESHOLD_ENHANCE << 26 & 0xc000000);
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(*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x38)) = val;
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(*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34)) =
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USB2_PHY_PLL_OFFSET_34;
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debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD);
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}
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int usb_save_phy_dev(unsigned int number, struct phy *phy)
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{
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int i;
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for (i = 0; i < AMLOGIC_CTR_COUNT; i++) {
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if (!ctr[i].usb_phys[number].dev) {
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ctr[i].usb_phys[number].dev = phy->dev;
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ctr[i].usb_phys[number].id = phy->id;
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} else {
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if (ctr[i].usb_phys[number].dev == phy->dev)
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break;
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}
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}
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return 0;
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}
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int usb2_phy_init(struct phy *phy)
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{
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struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev);
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struct u2p_aml_regs *u2p_aml_reg;
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u2p_r0_t dev_u2p_r0;
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u2p_r1_t dev_u2p_r1;
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int i, cnt;
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usb_save_phy_dev(0, phy);
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usb_enable_phy_pll(priv->base_addr);
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if (priv->usb_phy2_pll_base_addr[0] == PHY_20_BASE) {
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debug("priv->reset_addr is 0x%x\n", priv->reset_addr);
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*(volatile unsigned int *)(unsigned long)priv->reset_addr =
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(1 << USB_2_DRD_BIT) | (1 << USB_RESET_BIT);
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udelay(500);
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priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT;
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} else {
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debug("priv->reset_addr is 0x%x\n", priv->reset_addr);
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*(unsigned int *)(unsigned long)priv->reset_addr =
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(1 << USB2H_BIT) | (1 << USB_RESET_BIT);
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udelay(500);
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priv->usbphy_reset_bit[0] = PHY21_RESET_LEVEL_BIT;
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priv->usbphy_reset_bit[1] = PHY22_RESET_LEVEL_BIT;
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}
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for (i = 0; i < priv->u2_port_num; i++) {
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u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE));
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debug("u2p_aml_reg is 0x%x\n", (u32)(u64)u2p_aml_reg);
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dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0;
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dev_u2p_r0.b.host_device = 1;
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dev_u2p_r0.b.POR = 0;
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u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32;
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udelay(10);
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*(volatile unsigned int *)(unsigned long)priv->reset_addr = (1 << priv->usbphy_reset_bit[i]);
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udelay(50);
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/* wait for phy ready */
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dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
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cnt = 0;
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while (dev_u2p_r1.b.phy_rdy != 1) {
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dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
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/*we wait phy ready max 1ms, common is 100us*/
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if (cnt > 200) {
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break;
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} else {
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cnt++;
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udelay(5);
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}
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}
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}
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for (i = 0; i < priv->u2_port_num; i++) {
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debug("------set usb pll\n");
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set_usb_pll(priv->usb_phy2_pll_base_addr[i]);
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}
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return 0;
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}
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int usb2_phy_tuning(uint32_t phy2_pll_base, int port)
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{
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return 0;
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}
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/**************************************************************/
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/* device mode config */
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/**************************************************************/
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void usb_device_mode_init(int phy_num)
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{
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u2p_r0_t dev_u2p_r0;
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u2p_r1_t dev_u2p_r1;
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usb_r0_t dev_usb_r0;
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usb_r4_t dev_usb_r4;
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int cnt;
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u2p_aml_regs_t *u2p_aml_regs;
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usb_aml_regs_t *usb_aml_regs;
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unsigned int phy_base_addr, reset_addr;
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u2p_aml_regs = (u2p_aml_regs_t *)((unsigned long)(PHY_COMP_BASE));
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usb_aml_regs = (usb_aml_regs_t *)((ulong)(PHY_COMP_BASE + 0x80));
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phy_base_addr = PHY_20_BASE;
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reset_addr = RESET_BASE;
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printf("PHY2=%p,phy-base=0x%08x\n", u2p_aml_regs, phy_base_addr);
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//if ((*(volatile uint32_t *)(unsigned long)(phy_base_addr + 0x38)) != 0) {
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//usb_phy_tuning_reset(phy_num);
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//mdelay(150);
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//}
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//step 1: usb controller reset
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usb_reset(reset_addr, USB_RESET_BIT);
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// step 3: enable usb INT internal USB
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dev_usb_r0.d32 = usb_aml_regs->usb_r0;
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dev_usb_r0.b.u2d_ss_scaledown_mode = 0;
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dev_usb_r0.b.u2d_act = 1;
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usb_aml_regs->usb_r0 = dev_usb_r0.d32;
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// step 4: disable usb phy sleep
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dev_usb_r4.d32 = usb_aml_regs->usb_r4;
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dev_usb_r4.b.p21_SLEEPM0 = 1;
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usb_aml_regs->usb_r4 = dev_usb_r4.d32;
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// step 5: config phy21 device mode
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dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0;
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dev_u2p_r0.b.host_device = 0;
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dev_u2p_r0.b.POR = 0;
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u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32;
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udelay(10);
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//step 6: phy21 reset
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usb_reset(reset_addr, PHY20_RESET_LEVEL_BIT);
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udelay(50);
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// step 6: wait for phy ready
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dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
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cnt = 0;
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while ((dev_u2p_r1.d32 & 0x00000001) != 1) {
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dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
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if (cnt > 200) {
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break;
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} else {
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cnt++;
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udelay(5);
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}
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}
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//set_usb_phy21_pll();
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set_usb_pll(phy_base_addr);
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//--------------------------------------------------
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// ------------- usb phy21 initial end ----------
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//--------------------------------------------------
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}
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