677 lines
13 KiB
Devicetree
677 lines
13 KiB
Devicetree
/*
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* Copyright (c) 2016 Endless Computers, Inc.
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* Author: Carlo Caione <[email protected]>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "meson-txhd2-series.dtsi"
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#include <dt-bindings/gpio/meson-txhd2-gpio.h>
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#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
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#include <dt-bindings/pwm/pwm.h>
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#include <dt-bindings/pwm/meson.h>
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/ {
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compatible = "amlogic,meson-txhd2";
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vpu {
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compatible = "amlogic, vpu-t7";
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status = "okay";
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/*clocks = <&clkc CLKID_VAPB_MUX>,
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* <&clkc CLKID_VPU_INTR>,
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* <&clkc CLKID_VPU_P0_COMP>,
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* <&clkc CLKID_VPU_P1_COMP>,
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* <&clkc CLKID_VPU_MUX>;
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*clock-names = "vapb_clk",
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* "vpu_intr_gate",
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* "vpu_clk0",
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* "vpu_clk1",
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* "vpu_clk";
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*/
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clk_level = <7>;
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/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
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/* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
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};
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fb {
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status = "okay";
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logo_addr = "0x3f800000";
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};
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pinctrl_aobus: pinctrl@ff800014 {
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compatible = "amlogic,meson-txhd2-aobus-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio_ao: ao-bank@ff800014 {
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reg = <0x0 0xff800014 0x0 0x008>,
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<0x0 0xff800024 0x0 0x014>;
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reg-names = "mux","gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aobus 0 0 14>;
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};
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};
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pinctrl_test: pinctrl@ff80035c {
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compatible = "amlogic,meson-txhd2-testn-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio_test: test-bank@ff80035c {
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reg = <0x0 0xff80035c 0x0 0x4>,
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<0x0 0xff80035c 0x0 0x4>;
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reg-names = "mux", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_test 0 0 1>;
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};
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};
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i2c_gpio_0: i2c-gpio-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "i2c-gpio";
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status = "okay";
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gpios = <&gpio GPIOH_0 GPIO_ACTIVE_HIGH>, /* SDA */
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<&gpio GPIOH_1 GPIO_ACTIVE_HIGH>; /* CLK */
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i2c-gpio,delay-us = <5>;
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is_odpin = <1>;
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};
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pwm_ab: pwm@0xffd1b000 {
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compatible = "amlogic,g12a-ee-pwm";
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reg = <0x0 0xffd1b000 0x0 0x20>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_cd: pwm@0xffd1a000 {
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compatible = "amlogic,g12a-ee-pwm";
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reg = <0x0 0xffd1a000 0x0 0x20>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_ef: pwm@0xffd19000 {
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compatible = "amlogic,g12a-ee-pwm";
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reg = <0x0 0xffd19000 0x0 0x20>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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};
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ðmac {
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compatible = "amlogic,g12a-eth-dwmac";
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reg = <0x0 0xff3f0000 0x0 0x10000
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0x0 0xFF650000 0x0 0x8
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0x0 0xFF652000 0x0 0xa0>;
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reg-names = "eth_base", "eth_top", "eth_cfg";
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phy_cntl1 = <0x41054147>;
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internal_phy = <1>;
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mc_val = <0x4be04>;
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cali_val = <0x60000>;
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phy_pll_mode = <1>;
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//reset-gpios = <&gpio GPIOC_15 GPIO_ACTIVE_HIGH>;
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analog_ver = <1>; /*1:c1; 2:c2*/
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pll_val = <0x608200a0 0xea002000 0x00000150>;
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analog_val = <0x20200000 0x0000c000 0x00000023>;
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chip_num = <3>;
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//tx_amp_src = <0xfe005b30>;
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// clocks = <&clkc CLKID_ETH_CORE>,
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// <&clkc CLKID_FCLK_DIV2>,
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// <&clkc CLKID_MPLL2>;
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// clock-names = "stmmaceth", "clkin0", "clkin1";
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mdio0: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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};
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};
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&periphs {
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pinctrl_periphs: pinctrl@2c0 {
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compatible = "amlogic,meson-txhd2-periphs-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio: banks@2c0 {
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reg = <0x0 0x2c0 0x0 0x040>,
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<0x0 0x0e8 0x0 0x018>,
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<0x0 0x120 0x0 0x018>,
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<0x0 0x040 0x0 0x04c>;
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reg-names = "mux", "pull", "pull-enable", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_periphs 0 0 66>;
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};
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};
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eth-phy-mux {
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x15c 0x0 0x4>;
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mux-mask = <0xffffffff>;
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mdio-parent-bus = <&mdio0>;
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internal_mdio: mdio@e40908ff {
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reg = <0xe40908ff>;
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#address-cells = <1>;
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#size-cells = <0>;
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internal_phy: ethernet-phy@8 {
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compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
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reg = <8>;
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max-speed = <100>;
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};
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};
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external_mdio: mdio@2009087f {
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reg = <0x2009087f>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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&saradc {
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compatible = "amlogic,meson-txhd2-saradc", "amlogic,meson-saradc";
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clocks = <&xtal>,
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<&clkc CLKID_SARADC_MUX>,
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<&clkc CLKID_SARADC_DIV>,
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<&clkc CLKID_SAR_ADC_GATE>;
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clock-names = "xtal", "adc_mux", "adc_div", "adc_gate";
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};
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&sd_emmc_c {
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clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
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<&clkc CLKID_SD_EMMC_C_DIV>,
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<&clkc CLKID_SD_EMMC_C_GATE>,
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//<&clkc CLKID_FCLK_DIV2>,
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<&clkc CLKID_GP0_PLL>,
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<&clkc CLKID_XTAL>;
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clock-names = "mux", "div", "gate", "clkin", "xtal";
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};
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&nand {
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clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
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<&clkc CLKID_SD_EMMC_C_DIV>,
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<&clkc CLKID_SD_EMMC_C_GATE>,
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<&clkc CLKID_FCLK_DIV2>,
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<&clkc CLKID_XTAL>;
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clock-names = "mux", "div", "gate", "fdiv2", "xtal";
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};
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&spicc0 {
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clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>;
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clock-names = "async", "async-gate";
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assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>;
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assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
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assigned-clock-rates = <0>, <200000000>;
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//pm-id = PM_SPICC0;
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};
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&pinctrl_aobus {
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remote_input_ao_pins:remote_input_ao_pins {
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mux {
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groups = "remote_input_ao6";
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function = "remote";
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bias-disable;
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};
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};
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jtag_a_pins:jtag_a_pin {
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mux {
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groups = "jtag_clk_ao5",
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"jtag_tms_ao7",
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"jtag_tdi_ao3",
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"jtag_tdo_ao4";
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function = "jtag_ao";
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};
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};
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i2cAO_pins1:i2cAO_pins1 {
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mux {
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groups = "i2cm_ao_a_scl_ao4",
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"i2cm_ao_a_sda_ao5";
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function = "i2cm_ao_a";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2cAO_pins2:i2cAO_pins2 {
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mux {
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groups = "i2cm_ao_a_scl_ao10",
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"i2cm_ao_a_sda_ao11";
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function = "i2cm_ao_a";
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drive-strength = <3>;
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bias-disable;
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};
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};
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};
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&pinctrl_periphs {
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jtag_b_pins:jtag_b_pin {
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mux {
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groups = "jtag_clk_c4",
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"jtag_tms_c5",
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"jtag_tdi_c1",
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"jtag_tdo_c0";
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function = "jtag";
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};
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};
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i2c0_pins1:i2c0_pins1 {
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mux {
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groups = "i2cm_a_sda_dv4",
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"i2cm_a_scl_dv5";
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function = "i2cm_a";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c0_pins2:i2c0_pins2 {
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mux {
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groups = "i2cm_a_scl_h4",
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"i2cm_a_sda_h5";
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function = "i2cm_a";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c0_pins3:i2c0_pins3 {
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mux {
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groups = "i2cm_a_sda_z6",
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"i2cm_a_scl_z7";
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function = "i2cm_a";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c1_pins1:i2c1_pins1 {
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mux {
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groups = "i2cm_b_sda_dv0",
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"i2cm_b_scl_dv1";
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function = "i2cm_b";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c1_pins2:i2c1_pins2 {
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mux {
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groups = "i2cm_b_sda_z0",
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"i2cm_b_scl_z1";
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function = "i2cm_b";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c2_pins1:i2c2_pins1 {
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mux {
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groups = "i2cm_c_sda_c2",
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"i2cm_c_scl_c3";
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function = "i2cm_c";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c2_pins2:i2c2_pins2 {
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mux {
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groups = "i2cm_c_scl_h8",
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"i2cm_c_sda_h9";
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function = "i2cm_c";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c3_pins1:i2c3_pins1 {
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mux {
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groups = "i2cm_d_scl_h0",
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"i2cm_d_sda_h1";
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function = "i2cm_d";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c3_pins2:i2c3_pins2 {
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mux {
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groups = "i2cm_d_scl_h10",
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"i2cm_d_sda_h11";
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function = "i2cm_d";
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drive-strength = <3>;
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bias-disable;
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};
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};
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swd_a_pins:swd_a_pin {
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mux {
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groups = "swclk",
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"swdio";
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function = "sw";
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};
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};
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emmc_pins: emmc {
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mux {
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groups = "emmc_d0",
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"emmc_d1",
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"emmc_d2",
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"emmc_d3",
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"emmc_d4",
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"emmc_d5",
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"emmc_d6",
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"emmc_d7",
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"emmc_clk",
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"emmc_cmd";
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function = "emmc";
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bias-pull-up;
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input-enable;
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};
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mux1 {
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groups = "emmc_ds";
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function = "emmc";
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input-enable;
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bias-pull-down;
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};
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};
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emmc_clk_gate_pins: emmc_clk_gate {
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mux {
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groups = "emmc_clk";
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function = "emmc";
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bias-pull-down;
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};
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};
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all_nand_pins: all_nand_pins {
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mux {
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groups = "emmc_nand_d0",
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"emmc_nand_d1",
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"emmc_nand_d2",
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"emmc_nand_d3",
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"emmc_nand_d4",
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"emmc_nand_d5",
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"emmc_nand_d6",
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"emmc_nand_d7",
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"nand_ce0",
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"nand_ale",
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"nand_cle",
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"nand_wen_clk",
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"nand_ren_wr";
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function = "nand";
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input-enable;
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};
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};
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nand_cs_pins: nand_cs {
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mux {
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groups = "nand_ce0";
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function = "nand";
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};
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};
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sdcard_pins: sdcard {
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mux {
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groups = "sdcard_d0",
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"sdcard_d1",
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"sdcard_d2",
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"sdcard_d3",
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"sdcard_cmd";
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function = "sdcard";
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bias-pull-up;
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input-enable;
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drive-strength = <4>;
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};
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mux1 {
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groups ="sdcard_clk";
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function = "sdcard";
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bias-pull-up;
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output-high;
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drive-strength = <4>;
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};
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};
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sdcard_clk_gate_pins: sdcard_clk_gate {
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mux {
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groups = "sdcard_clk";
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function = "sdcard";
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bias-pull-down;
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};
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};
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to_sduart_pins: to_sduart_pins{
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mux {
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groups = "uart_b_rx_c", "uart_b_tx_c";
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function = "uart_b";
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bias-pull-up;
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input-enable;
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};
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};
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sd_to_uart_pins: sd_to_uart_pins{
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mux {
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groups = "uart_b_rx_d", "uart_b_tx_d";
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function = "uart_b";
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bias-pull-up;
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input-enable;
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};
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};
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spicc0_pins_c: spicc0_pins_c {
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mux {
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groups = "spi_mosi_a_c8",
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"spi_miso_a_c9",
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"spi_clk_a_c10";
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|
function = "spi";
|
|
drive-strength = <3>;
|
|
};
|
|
};
|
|
|
|
spicc0_pins_dv: spicc0_pins_dv {
|
|
mux {
|
|
groups = "spi_mosi_a_dv8",
|
|
"spi_miso_a_dv7",
|
|
"spi_ss0_a_dv6",
|
|
"spi_clk_a_dv9";
|
|
function = "spi";
|
|
drive-strength = <3>;
|
|
};
|
|
};
|
|
|
|
spifc_pins: spifc_pins {
|
|
mux {
|
|
groups = "spif_mo",
|
|
"spif_mi",
|
|
"spif_clk",
|
|
"spif_hold",
|
|
"spif_wp";
|
|
function = "spif";
|
|
drive-strength = <3>;
|
|
};
|
|
};
|
|
|
|
pwm_a_pins: pwm_a_pins {
|
|
mux {
|
|
groups = "pwm_a";
|
|
function = "pwm_a";
|
|
};
|
|
};
|
|
|
|
pwm_b_pins1: pwm_b_pins1 {
|
|
mux {
|
|
groups = "pwm_b_z";
|
|
function = "pwm_b";
|
|
};
|
|
};
|
|
|
|
pwm_b_pins2: pwm_b_pins2 {
|
|
mux {
|
|
groups = "pwm_b_h";
|
|
function = "pwm_b";
|
|
};
|
|
};
|
|
|
|
pwm_c_pins: pwm_c_pins {
|
|
mux {
|
|
groups = "pwm_c";
|
|
function = "pwm_c";
|
|
};
|
|
};
|
|
|
|
pwm_d_pins1: pwm_d_pins1 {
|
|
mux {
|
|
groups = "pwm_d_z";
|
|
function = "pwm_d";
|
|
};
|
|
};
|
|
|
|
pwm_d_pins2: pwm_d_pins2 {
|
|
mux {
|
|
groups = "pwm_d_h5";
|
|
function = "pwm_d";
|
|
};
|
|
};
|
|
|
|
pwm_d_pins3: pwm_d_pins3 {
|
|
mux {
|
|
groups = "pwm_d_h12";
|
|
function = "pwm_d";
|
|
};
|
|
};
|
|
|
|
pwm_d_pins4: pwm_d_pins4 {
|
|
mux {
|
|
groups = "pwm_d_m1";
|
|
function = "pwm_d";
|
|
};
|
|
};
|
|
|
|
pwm_d_pins5: pwm_d_pins5 {
|
|
mux {
|
|
groups = "pwm_d_m23";
|
|
function = "pwm_d";
|
|
};
|
|
};
|
|
|
|
pwm_e_pins1: pwm_e_pins1 {
|
|
mux {
|
|
groups = "pwm_e_z";
|
|
function = "pwm_e";
|
|
};
|
|
};
|
|
|
|
pwm_e_pins2: pwm_e_pins2 {
|
|
mux {
|
|
groups = "pwm_e_h";
|
|
function = "pwm_e";
|
|
};
|
|
};
|
|
|
|
pwm_e_pins3: pwm_e_pins3 {
|
|
mux {
|
|
groups = "pwm_e_m";
|
|
function = "pwm_e";
|
|
};
|
|
};
|
|
|
|
pwm_f_pins1: pwm_f_pins1 {
|
|
mux {
|
|
groups = "pwm_f_z";
|
|
function = "pwm_f";
|
|
};
|
|
};
|
|
|
|
pwm_f_pins2: pwm_f_pins2 {
|
|
mux {
|
|
groups = "pwm_f_c";
|
|
function = "pwm_f";
|
|
};
|
|
};
|
|
|
|
pwm_f_pins3: pwm_f_pins3 {
|
|
mux {
|
|
groups = "pwm_f_m";
|
|
function = "pwm_f";
|
|
};
|
|
};
|
|
|
|
external_eth_rmii_pins: external_eth_rmii_pins {
|
|
mux {
|
|
groups = "eth_mdio_c",
|
|
"eth_mdc_c",
|
|
"eth_rgmii_rx_clk_c",
|
|
"eth_rx_dv_c",
|
|
"eth_rxd0_c",
|
|
"eth_rxd1_c",
|
|
"eth_txen_c",
|
|
"eth_txd0_c",
|
|
"eth_txd1_c";
|
|
function = "eth";
|
|
drive-strength = <3>;
|
|
};
|
|
};
|
|
|
|
external_eth_rgmii_pins: external_eth_rgmii_pins {
|
|
mux {
|
|
groups = "eth_mdio_c",
|
|
"eth_mdc_c",
|
|
"eth_rgmii_rx_clk_c",
|
|
"eth_rx_dv_c",
|
|
"eth_rxd0_c",
|
|
"eth_rxd1_c",
|
|
"eth_rxd2_rgmii_c",
|
|
"eth_rxd3_rgmii_c",
|
|
"eth_rgmii_tx_clk_c",
|
|
"eth_txen_c",
|
|
"eth_txd0_c",
|
|
"eth_txd1_c",
|
|
"eth_txd2_rgmii_c",
|
|
"eth_txd3_rgmii_c";
|
|
function = "eth";
|
|
drive-strength = <3>;
|
|
};
|
|
};
|
|
};
|