714 lines
13 KiB
Devicetree
714 lines
13 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#include "meson-a4-series.dtsi"
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#include <dt-bindings/gpio/meson-a4-gpio.h>
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#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
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#include <dt-bindings/pwm/pwm.h>
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#include <dt-bindings/pwm/meson.h>
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/ {
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compatible = "amlogic,meson-a4";
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vpu: vpu {
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compatible = "amlogic, vpu-a4";
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status = "okay";
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/*clocks = <&clkc CLKID_VAPB_MUX>,
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* <&clkc CLKID_VPU_INTR>,
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* <&clkc CLKID_VPU_P0_COMP>,
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* <&clkc CLKID_VPU_P1_COMP>,
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* <&clkc CLKID_VPU_MUX>;
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*clock-names = "vapb_clk",
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* "vpu_intr_gate",
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* "vpu_clk0",
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* "vpu_clk1",
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* "vpu_clk";
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*/
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clk_level = <7>;
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/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
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/* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
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};
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fb {
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status = "okay";
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logo_addr = "0x7f800000";
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};
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pinctrl_periphs: pinctrl@fe004000 {
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compatible = "amlogic,meson-a4-periphs-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio: bank@fe004000 {
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reg = <0x0 0xfe004000 0x0 0x0050>,
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<0x0 0xfe0040c0 0x0 0x0220>;
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reg-names = "mux",
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"gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_periphs 0 0 73>;
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};
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};
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pinctrl_aobus: pinctrl@fe08e700 {
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compatible = "amlogic,meson-a4-aobus-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio_ao: bank@fe08e700 {
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reg = <0x0 0xfe08e700 0x0 0x04>,
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<0x0 0xfe08e704 0x0 0x60>;
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reg-names = "mux", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aobus 0 0 8>;
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};
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};
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i2c_gpio_0: i2c-gpio-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "i2c-gpio";
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status = "okay";
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//gpios = <&gpio GPIOH_0 GPIO_ACTIVE_HIGH>, /* SDA */
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// <&gpio GPIOH_1 GPIO_ACTIVE_HIGH>; /* CLK */
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i2c-gpio,delay-us = <5>;
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is_odpin = <1>;
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};
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pwm_ab: pwm@fe058000 {
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compatible = "amlogic,meson-v2-pwm";
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reg = <0x0 0xfe058000 0x0 0x20>,
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<0x0 0xfe000180 0x0 0x04>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_cd: pwm@fe05a000 {
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compatible = "amlogic,meson-v2-pwm";
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reg = <0x0 0xfe05a000 0x0 0x20>,
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<0x0 0xfe000184 0x0 0x04>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_ef: pwm@fe05c000 {
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compatible = "amlogic,meson-v2-pwm";
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reg = <0x0 0xfe05c000 0x0 0x20>,
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<0x0 0xfe000188 0x0 0x04>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_gh: pwm@fe05e000 {
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compatible = "amlogic,meson-v2-pwm";
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reg = <0x0 0xfe05e000 0x0 0x20>,
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<0x0 0xfe00018c 0x0 0x04>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_ij: pwm@fe060000 {
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compatible = "amlogic,meson-v2-pwm";
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reg = <0x0 0xfe060000 0x0 0x20>,
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<0x0 0xfe000190 0x0 0x04>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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};
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ðmac {
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compatible = "amlogic,g12a-eth-dwmac";
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reg = <0x0 0xfdc00000 0x0 0x10000
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0x0 0xFE024000 0x0 0x8
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0x0 0xFE028000 0x0 0xa0>;
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reg-names = "eth_base", "eth_top", "eth_cfg";
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phy_cntl1 = <0x41054147>;
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internal_phy = <1>;
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mc_val = <0x4be04>;
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pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
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analog_val = <0x20200000 0x0000c000 0x00000023>;
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chip_num = <3>;
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cali_val = <0x80000>;
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//tx_amp_src = <0xfe005b30>;
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// clocks = <&clkc CLKID_ETH_CORE>,
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// <&clkc CLKID_FCLK_DIV2>,
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// <&clkc CLKID_MPLL2>;
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// clock-names = "stmmaceth", "clkin0", "clkin1";
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mdio0: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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};
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};
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&periphs {
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eth-phy-mux {
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x15c 0x0 0x4>;
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mux-mask = <0xffffffff>;
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mdio-parent-bus = <&mdio0>;
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external_mdio: mdio@2009087f {
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reg = <0x2009087f>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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&saradc {
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compatible = "amlogic,meson-a4-saradc", "amlogic,meson-saradc";
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clocks = <&xtal>,
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<&clkc CLKID_SARADC_SEL>,
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<&clkc CLKID_SARADC_DIV>,
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<&clkc CLKID_SARADC>;
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clock-names = "xtal", "adc_mux", "adc_div", "adc_gate";
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};
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&sd_emmc_a {
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clocks = <&clkc CLKID_SD_EMMC_A_SEL>,
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<&clkc CLKID_SD_EMMC_A_DIV>,
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<&clkc CLKID_SD_EMMC_A>,
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<&clkc CLKID_FCLK_DIV2>,
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<&clkc CLKID_XTAL>;
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clock-names = "mux", "div", "gate", "clkin", "xtal";
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};
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&sd_emmc_b {
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//clocks = <&clkc CLKID_SD_EMMC_B_MUX>,
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// <&clkc CLKID_SD_EMMC_B_DIV>,
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// <&clkc CLKID_SD_EMMC_B_GATE>,
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// <&clkc CLKID_FCLK_DIV2>,
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// <&clkc CLKID_XTAL>;
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// clock-names = "mux", "div", "gate", "clkin", "xtal";
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};
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&sd_emmc_c {
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clocks = <&clkc CLKID_SD_EMMC_C_SEL>,
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<&clkc CLKID_SD_EMMC_C_DIV>,
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<&clkc CLKID_SD_EMMC_C>,
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<&clkc CLKID_GP0_PLL>,
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<&clkc CLKID_XTAL>;
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clock-names = "mux", "div", "gate", "clkin", "xtal";
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};
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&nand {
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clocks = <&clkc CLKID_SD_EMMC_C_SEL>,
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<&clkc CLKID_SD_EMMC_C_DIV>,
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<&clkc CLKID_SD_EMMC_C>,
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<&clkc CLKID_FCLK_DIV2>,
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<&clkc CLKID_XTAL>;
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clock-names = "mux", "div", "gate", "fdiv2", "xtal";
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};
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&spicc0 {
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clocks = <&clkc CLKID_SPICC_0_DIV>, <&clkc CLKID_SPICC_0>;
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clock-names = "spi_clk", "sys_clk";
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assigned-clocks = <&clkc CLKID_SPICC_0_SEL>, <&clkc CLKID_SPICC_0_DIV>;
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assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
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assigned-clock-rates = <0>, <500000000>;
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};
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&spicc1 {
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clocks = <&clkc CLKID_SPICC_1_DIV>, <&clkc CLKID_SPICC_1>;
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clock-names = "spi_clk", "sys_clk";
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assigned-clocks = <&clkc CLKID_SPICC_1_SEL>, <&clkc CLKID_SPICC_1_DIV>;
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assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
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assigned-clock-rates = <0>, <500000000>;
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};
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&pinctrl_periphs {
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remote_input_ao_pins:remote_input_ao_pins {
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mux {
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groups = "remote_in";
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function = "remote_in";
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bias-disable;
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};
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};
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i2c0_pins1:i2c0_pins1 {
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mux {
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groups = "i2c0_sda_e0",
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"i2c0_scl_e1";
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function = "i2c0";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c0_pins2:i2c0_pins2 {
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mux {
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groups = "i2c0_sda_x16",
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"i2c0_scl_x17";
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function = "i2c0";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c0_pins3:i2c0_pins3 {
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mux {
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groups = "i2c0_sda_t21",
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"i2c0_scl_t22";
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function = "i2c0";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c1_pins1:i2c1_pins1 {
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mux {
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groups = "i2c1_sda_d2",
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"i2c1_scl_d3";
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function = "i2c1";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c1_pins2:i2c1_pins2 {
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mux {
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groups = "i2c1_sda_d10",
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"i2c1_scl_d11";
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function = "i2c1";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c2_pins1:i2c2_pins1 {
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mux {
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groups = "i2c2_sda_d14",
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"i2c2_scl_d15";
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function = "i2c2";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c2_pins2:i2c2_pins2 {
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mux {
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groups = "i2c2_sda_t11",
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"i2c2_scl_t12";
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function = "i2c2";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c3_pins1:i2c3_pins1 {
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mux {
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groups = "i2c3_sda_d12",
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"i2c3_scl_d13";
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function = "i2c3";
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drive-strength = <3>;
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bias-disable;
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};
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};
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i2c3_pins2:i2c3_pins2 {
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mux {
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groups = "i2c3_sda_t0",
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"i2c3_scl_t1";
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function = "i2c3";
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drive-strength = <3>;
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bias-disable;
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};
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};
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jtag_a_pins:jtag_a_pin {
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mux {
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groups = "jtag_1_clk",
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"jtag_1_tms",
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"jtag_1_tdi",
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"jtag_1_tdo";
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function = "jtag_1";
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};
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};
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swd_a_pins:swd_a_pin {
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mux {
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groups = "swclk",
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"swdio";
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function = "sw";
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};
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};
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emmc_pins: emmc {
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mux {
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groups = "emmc_nand_d0",
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"emmc_nand_d1",
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"emmc_nand_d2",
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"emmc_nand_d3",
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"emmc_nand_d4",
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"emmc_nand_d5",
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"emmc_nand_d6",
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"emmc_nand_d7",
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"emmc_clk",
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"emmc_cmd";
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function = "emmc";
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bias-pull-up;
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input-enable;
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};
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mux1 {
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groups = "emmc_nand_ds";
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function = "emmc";
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input-enable;
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bias-pull-down;
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};
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};
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emmc_clk_gate_pins: emmc_clk_gate {
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mux {
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groups = "emmc_clk";
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function = "emmc";
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bias-pull-down;
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};
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};
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all_nand_pins: all_nand_pins {
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mux {
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groups = "emmc_nand_d0",
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"emmc_nand_d1",
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"emmc_nand_d2",
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"emmc_nand_d3",
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"emmc_nand_d4",
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"emmc_nand_d5",
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"emmc_nand_d6",
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"emmc_nand_d7",
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"nand_ce0",
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"nand_ale",
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"nand_cle",
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"nand_wen_clk",
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"nand_ren_wr";
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function = "nand";
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input-enable;
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};
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};
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nand_cs_pins: nand_cs {
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mux {
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groups = "nand_ce0";
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function = "nand";
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};
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};
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sdcard_pins: sdcard {
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mux {
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groups = "sdio_d0",
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"sdio_d1",
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"sdio_d2",
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"sdio_d3",
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"sdio_cmd";
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function = "sdio";
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bias-pull-up;
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input-enable;
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drive-strength = <4>;
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};
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mux1 {
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groups ="sdio_clk";
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function = "sdio";
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bias-pull-up;
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output-high;
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drive-strength = <4>;
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};
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};
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sdcard_clk_gate_pins: sdcard_clk_gate {
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mux {
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groups = "sdio_clk";
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function = "sdio";
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bias-pull-down;
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};
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};
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to_sduart_pins: to_sduart_pins{
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mux {
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groups = "uart_b_rx_c", "uart_b_tx_c";
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function = "uart_b";
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bias-pull-up;
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input-enable;
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};
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};
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sd_to_uart_pins: sd_to_uart_pins{
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mux {
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groups = "uart_b_rx_d", "uart_b_tx_d";
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function = "uart_b";
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bias-pull-up;
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input-enable;
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};
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};
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spicc0_pins_x: spicc0_pins_x {
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mux {
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groups = "spi_a_mosi_x7",
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"spi_a_miso_x8",
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"spi_a_ss0_x9",
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"spi_a_clk_x10";
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function = "spi_a";
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drive-strength = <2>;
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};
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};
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spicc0_pins_t: spicc0_pins_t {
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mux {
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groups = "spi_a_dq2",
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"spi_a_dq3",
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"spi_a_clk_t13",
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"spi_a_mosi_t14",
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"spi_a_miso_t15",
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"spi_a_ss0_t16";
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function = "spi_a";
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drive-strength = <2>;
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};
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};
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spicc1_pins_x: spicc1_pins_x {
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mux {
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groups = "spi_b_mosi_x14",
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"spi_b_ss0_x15",
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"spi_b_clk_x16",
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"spi_b_miso_x17";
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function = "spi_b";
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drive-strength = <2>;
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};
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};
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spicc1_pins_d: spicc1_pins_d {
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mux {
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groups = "spi_b_miso_d2",
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"spi_b_mosi_d3",
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"spi_b_clk_d4",
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"spi_b_ss0_d5";
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function = "spi_b";
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drive-strength = <2>;
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};
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};
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spicc1_pins_t: spicc1_pins_t {
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mux {
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groups = "spi_b_dq2",
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"spi_b_dq3",
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"spi_b_clk_t5",
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"spi_b_mosi_t6",
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"spi_b_miso_t7",
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"spi_b_ss0_t8";
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function = "spi_b";
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drive-strength = <2>;
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};
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};
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spi_nfc_pins: spi_nfc_pins {
|
|
mux {
|
|
groups = "spinf_mo_d0",
|
|
"spinf_mi_d1",
|
|
"spinf_wp_d2",
|
|
"spinf_hold_d3",
|
|
"spinf_d4",
|
|
"spinf_d5",
|
|
"spinf_d6",
|
|
"spinf_d7",
|
|
"spinf_clk",
|
|
"spinf_cs0";
|
|
function = "spinf";
|
|
drive-strength = <3>;
|
|
};
|
|
};
|
|
|
|
pwm_a_pins: pwm_a_pins {
|
|
mux {
|
|
groups = "pwm_a_d";
|
|
function = "pwm_a";
|
|
};
|
|
};
|
|
|
|
pwm_b_pins1: pwm_b_pins1 {
|
|
mux {
|
|
groups = "pwm_b_d";
|
|
function = "pwm_b";
|
|
};
|
|
};
|
|
|
|
pwm_b_pins2: pwm_b_pins2 {
|
|
mux {
|
|
groups = "pwm_b_x";
|
|
function = "pwm_b";
|
|
};
|
|
};
|
|
|
|
pwm_c_pins1: pwm_c_pins1 {
|
|
mux {
|
|
groups = "pwm_c_d";
|
|
function = "pwm_c";
|
|
};
|
|
};
|
|
|
|
pwm_c_pins2: pwm_c_pins2 {
|
|
mux {
|
|
groups = "pwm_c_x";
|
|
function = "pwm_c";
|
|
};
|
|
};
|
|
|
|
pwm_d_pins1: pwm_d_pins1 {
|
|
mux {
|
|
groups = "pwm_d_d";
|
|
function = "pwm_d";
|
|
};
|
|
};
|
|
|
|
pwm_d_pins2: pwm_d_pins2 {
|
|
mux {
|
|
groups = "pwm_d_h";
|
|
function = "pwm_d";
|
|
};
|
|
};
|
|
|
|
pwm_e_pins1: pwm_e_pins1 {
|
|
mux {
|
|
groups = "pwm_e_x";
|
|
function = "pwm_e";
|
|
};
|
|
};
|
|
|
|
pwm_e_pins2: pwm_e_pins2 {
|
|
mux {
|
|
groups = "pwm_e_z";
|
|
function = "pwm_e";
|
|
};
|
|
};
|
|
|
|
pwm_f_pins1: pwm_f_pins1 {
|
|
mux {
|
|
groups = "pwm_f_x";
|
|
function = "pwm_f";
|
|
};
|
|
};
|
|
|
|
pwm_f_pins2: pwm_f_pins2 {
|
|
mux {
|
|
groups = "pwm_f_z";
|
|
function = "pwm_f";
|
|
};
|
|
};
|
|
|
|
pwm_g_pins1: pwm_g_pins1 {
|
|
mux {
|
|
groups = "pwm_g_d";
|
|
function = "pwm_g";
|
|
};
|
|
};
|
|
|
|
pwm_g_pins2: pwm_g_pins2 {
|
|
mux {
|
|
groups = "pwm_g_z";
|
|
function = "pwm_g";
|
|
};
|
|
};
|
|
|
|
pwm_h_pins: pwm_h_pins {
|
|
mux {
|
|
groups = "pwm_h";
|
|
function = "pwm_h";
|
|
};
|
|
};
|
|
|
|
pwm_i_pins1: pwm_i_pins1 {
|
|
mux {
|
|
groups = "pwm_i_d";
|
|
function = "pwm_i";
|
|
};
|
|
};
|
|
|
|
pwm_i_pins2: pwm_i_pins2 {
|
|
mux {
|
|
groups = "pwm_i_h";
|
|
function = "pwm_i";
|
|
};
|
|
};
|
|
|
|
pwm_j_pins: pwm_j_pins {
|
|
mux {
|
|
groups = "pwm_j";
|
|
function = "pwm_j";
|
|
};
|
|
};
|
|
|
|
pwm_a_hiz_pins: pwm_a_hiz_pins {
|
|
mux {
|
|
groups = "pwm_a_hiz";
|
|
function = "pwm_a_hiz";
|
|
};
|
|
};
|
|
|
|
pwm_b_hiz_pins: pwm_b_hiz_pins {
|
|
mux {
|
|
groups = "pwm_b_hiz";
|
|
function = "pwm_b_hiz";
|
|
};
|
|
};
|
|
|
|
pwm_c_hiz_pins: pwm_c_hiz_pins {
|
|
mux {
|
|
groups = "pwm_c_hiz";
|
|
function = "pwm_b_hiz";
|
|
};
|
|
};
|
|
|
|
pwm_g_hiz_pins: pwm_g_hiz_pins {
|
|
mux {
|
|
groups = "pwm_g_hiz";
|
|
function = "pwm_g_hiz";
|
|
};
|
|
};
|
|
|
|
external_eth_rmii_pins: external_eth_rmii_pins {
|
|
mux {
|
|
groups = "eth_mdio",
|
|
"eth_mdc",
|
|
"eth_rgmii_rx_clk",
|
|
"eth_rx_dv",
|
|
"eth_rxd0",
|
|
"eth_rxd1",
|
|
"eth_txen",
|
|
"eth_txd0",
|
|
"eth_txd1";
|
|
function = "eth";
|
|
drive-strength = <3>;
|
|
};
|
|
};
|
|
|
|
external_eth_rgmii_pins: external_eth_rgmii_pins {
|
|
mux {
|
|
groups = "eth_mdio",
|
|
"eth_mdc",
|
|
"eth_rgmii_rx_clk",
|
|
"eth_rx_dv",
|
|
"eth_rxd0",
|
|
"eth_rxd1",
|
|
"eth_rxd2_rgmii",
|
|
"eth_rxd3_rgmii",
|
|
"eth_rgmii_tx_clk",
|
|
"eth_txen",
|
|
"eth_txd0",
|
|
"eth_txd1",
|
|
"eth_txd2_rgmii",
|
|
"eth_txd3_rgmii";
|
|
function = "eth";
|
|
drive-strength = <3>;
|
|
};
|
|
};
|
|
};
|