53 lines
1.3 KiB
C
53 lines
1.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* include/amlogic/spifc.h
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*
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* Copyright (C) 2020 Amlogic, Inc. All rights reserved.
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*
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*/
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#ifndef __SPIFC_H__
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#define __SPIFC_H__
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#define SPIFC_DEFAULT_CLK_RATE 166666666
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/*
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* @reg: controller registers address.
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* @mem_map: memory_mapped for read operations.
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* @clk_get(): callback to get spifc clk pointer.
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* ret: should be "struct clk *"
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* dev: should be "struct udevice *"
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* @clk_get_rate():
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* @clk_enable():
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* @pinctrl_get(): callback to get spifc pinctrl pointer.
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* ret: should be "struct pinctrl *"
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* dev: should be "struct udevice *"
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* @num_chipselect:
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* @cs_gpios:
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*/
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/*
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* spifc driver will use the default clk81 rate 1666666666
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* if without following platform callbacks.
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static void* spifc_clk_get(void *dev, char *name)
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{ return NULL; }
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static int spifc_clk_get_rate(void *clk)
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{ return 1666666666; }
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static int spifc_clk_enable(void *clk, bool enable)
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{ return 0; }
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static void* spifc_pinctrl_get(void *dev, char *name)
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{ return NULL; }
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*/
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struct spifc_platdata {
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ulong reg;
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ulong mem_map;
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void *(*clk_get)(void *dev, char *name);
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int (*clk_get_rate)(void *clk);
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int (*clk_enable)(void *clk, bool enable);
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void *(*pinctrl_get)(void *dev, char *name);
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int (*pinctrl_enable)(void *pinctrl, bool enable);
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int num_chipselect;
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int *cs_gpios;
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};
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#endif /* __SPIFC_H__ */ |