278 lines
8.4 KiB
C
278 lines
8.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* drivers/vpu/aml_vpu_ctrl.h
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*
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* Copyright (C) 2020 Amlogic, Inc. All rights reserved.
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*
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*/
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#ifndef __VPU_CTRL_H__
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#define __VPU_CTRL_H__
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#include "aml_vpu.h"
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/* #define LIMIT_VPU_CLK_LOW */
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/* ************************************************ */
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/* VPU frequency table, important. DO NOT modify!! */
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/* ************************************************ */
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/* fixed pll frequency */
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#define FCLK_2000M 2000 /* unit: MHz */
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/* GXBB */
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/* freq max=666M, default=666M */
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#define CLK_LEVEL_DFT_GXBB 7
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#define CLK_LEVEL_MAX_GXBB 8
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/* GXTVBB */
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/* freq max=666M, default=666M */
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#define CLK_LEVEL_DFT_GXTVBB 7
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#define CLK_LEVEL_MAX_GXTVBB 8
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/* GXL */
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/* freq max=666M, default=666M */
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#define CLK_LEVEL_DFT_GXL 7
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#define CLK_LEVEL_MAX_GXL 8
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/* GXM */
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/* freq max=666M, default=666M */
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#define CLK_LEVEL_DFT_GXM 7
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#define CLK_LEVEL_MAX_GXM 8
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/* TXL */
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/* freq max=666M, default=666M */
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#define CLK_LEVEL_DFT_TXL 7
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#define CLK_LEVEL_MAX_TXL 8
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/* TXLX */
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/* freq max=666M, default=666M */
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#define CLK_LEVEL_DFT_TXLX 7
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#define CLK_LEVEL_MAX_TXLX 8
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/* AXG */
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/* freq max=250M, default=250M */
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#define CLK_LEVEL_DFT_AXG 3
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#define CLK_LEVEL_MAX_AXG 4
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/* TXHD */
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/* freq max=400M, default=400M */
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#define CLK_LEVEL_DFT_TXHD 5
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#define CLK_LEVEL_MAX_TXHD 6
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/* G12A */
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/* freq max=666M, default=666M */
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#define CLK_LEVEL_DFT_G12A 7
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#define CLK_LEVEL_MAX_G12A 8
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/* T5D */
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/* freq max=400M, default=400M */
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#define CLK_LEVEL_DFT_T5D 5
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#define CLK_LEVEL_MAX_T5D 6
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/* vpu clk setting */
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enum vpu_mux_e {
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FCLK_DIV4 = 0,
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FCLK_DIV3,
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FCLK_DIV5,
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FCLK_DIV7,
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MPLL_CLK1,
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VID_PLL_CLK,
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VID2_PLL_CLK,
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GPLL_CLK,
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FCLK_DIV_MAX,
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};
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static struct fclk_div_s fclk_div_table_gxb[] = {
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/* id, mux, div */
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{FCLK_DIV4, 0, 4},
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{FCLK_DIV3, 1, 3},
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{FCLK_DIV5, 2, 5},
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{FCLK_DIV7, 3, 7},
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{FCLK_DIV_MAX, 8, 1},
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};
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static struct fclk_div_s fclk_div_table_g12a[] = {
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/* id, mux, div */
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{FCLK_DIV3, 0, 3},
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{FCLK_DIV4, 1, 4},
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{FCLK_DIV5, 2, 5},
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{FCLK_DIV7, 3, 7},
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{FCLK_DIV_MAX, 8, 1},
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};
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static struct vpu_clk_s vpu_clk_table[] = {
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/* frequency clk_mux div */
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{100000000, FCLK_DIV5, 3}, /* 0 */
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{166667000, FCLK_DIV3, 3}, /* 1 */
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{200000000, FCLK_DIV5, 1}, /* 2 */
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{250000000, FCLK_DIV4, 1}, /* 3 */
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{333333000, FCLK_DIV3, 1}, /* 4 */
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{400000000, FCLK_DIV5, 0}, /* 5 */
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{500000000, FCLK_DIV4, 0}, /* 6 */
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{666667000, FCLK_DIV3, 0}, /* 7 */
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{696000000, GPLL_CLK, 0}, /* 8 */ /* invalid */
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{850000000, GPLL_CLK, 0}, /* 9 */ /* invalid */
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};
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/* ******************************************************* */
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/* VPU memory power down table */
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/* ******************************************************* */
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static struct vpu_ctrl_s vpu_mem_pd_gxb[] = {
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/* reg, val, bit, len */
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{HHI_VPU_MEM_PD_REG0, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG1, 1, 0, 32},
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{VPU_REG_END, 0, 0, 0},
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};
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static struct vpu_ctrl_s vpu_mem_pd_axg[] = {
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/* reg, val, bit, len */
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{HHI_VPU_MEM_PD_REG0, 1, 0, 32},
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{VPU_REG_END, 0, 0, 0},
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};
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static struct vpu_ctrl_s vpu_mem_pd_txhd[] = {
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/* reg, val, bit, len */
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{HHI_VPU_MEM_PD_REG0, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG1, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG2, 1, 2, 2}, /* tcon memory */
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{VPU_REG_END, 0, 0, 0},
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};
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static struct vpu_ctrl_s vpu_mem_pd_g12a[] = {
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/* reg, val, bit, len */
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{HHI_VPU_MEM_PD_REG0, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG1, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG2, 1, 0, 2},
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{HHI_VPU_MEM_PD_REG2, 1, 4, 14},
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{HHI_VPU_MEM_PD_REG2, 1, 30, 2},
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{VPU_REG_END, 0, 0, 0},
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};
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static struct vpu_ctrl_s vpu_mem_pd_g12b[] = {
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/* reg, val, bit, len */
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{HHI_VPU_MEM_PD_REG0, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG1, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG2, 1, 0, 2},
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{HHI_VPU_MEM_PD_REG2, 1, 4, 14},
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{HHI_VPU_MEM_PD_REG2, 1, 22, 2},
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{HHI_VPU_MEM_PD_REG2, 1, 30, 2},
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{VPU_REG_END, 0, 0, 0},
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};
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static struct vpu_ctrl_s vpu_mem_pd_tl1[] = {
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/* reg, val, bit, len */
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{HHI_VPU_MEM_PD_REG0, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG1, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG2, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG3, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG4, 1, 0, 4},
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{VPU_REG_END, 0, 0, 0},
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};
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static struct vpu_ctrl_s vpu_mem_pd_tm2[] = {
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/* reg, val, bit, len */
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{HHI_VPU_MEM_PD_REG0, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG1, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG2, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG3, 1, 0, 32},
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{HHI_VPU_MEM_PD_REG4, 1, 0, 8},
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{VPU_REG_END, 0, 0, 0},
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};
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/* ******************************************************* */
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/* VPU_HDMI POWER */
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/* ******************************************************* */
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static struct vpu_ctrl_s vpu_pwr_gxb[] = {
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/* reg, val, bit, len */
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{AO_RTI_GEN_PWR_SLEEP0, 1, 8, 1},
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{VPU_REG_END, 0, 0, 0},
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};
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/* ******************************************************* */
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/* VPU_HDMI ISO */
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/* ******************************************************* */
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static struct vpu_ctrl_s vpu_iso_gxb[] = {
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/* reg, val, bit, len */
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{AO_RTI_GEN_PWR_SLEEP0, 1, 9, 1},
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{VPU_REG_END, 0, 0, 0},
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};
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static struct vpu_ctrl_s vpu_iso_sm1[] = {
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/* reg, val, bit, len */
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{AO_RTI_GEN_PWR_ISO0, 1, 8, 1},
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{VPU_REG_END, 0, 0, 0},
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};
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/* ******************************************************* */
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/* VPU module init table */
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/* ******************************************************* */
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static struct vpu_ctrl_s vpu_module_init_gxm[] = {
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/* reg, val, bit, len */
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{DOLBY_CORE1_CLKGATE_CTRL, 0x55555555, 0, 32},
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{DOLBY_CORE2A_CLKGATE_CTRL, 0x55555555, 0, 32},
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{DOLBY_CORE3_CLKGATE_CTRL, 0x55555555, 0, 32},
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{VPU_REG_END, 0, 0, 0},
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};
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static struct vpu_ctrl_s vpu_module_init_txlx[] = {
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/* reg, val, bit, len */
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{DOLBY_TV_CLKGATE_CTRL, 1, 10, 2},
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{DOLBY_TV_CLKGATE_CTRL, 1, 2, 2},
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{DOLBY_TV_CLKGATE_CTRL, 1, 4, 2},
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{DOLBY_CORE2A_CLKGATE_CTRL, 1, 10, 2},
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{DOLBY_CORE2A_CLKGATE_CTRL, 1, 2, 2},
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{DOLBY_CORE2A_CLKGATE_CTRL, 1, 4, 2},
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{DOLBY_CORE3_CLKGATE_CTRL, 0, 1, 1},
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{DOLBY_CORE3_CLKGATE_CTRL, 1, 2, 2},
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{VPU_REG_END, 0, 0, 0},
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};
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static struct vpu_ctrl_s vpu_module_init_g12a[] = {
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/* reg, val, bit, len */
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{DOLBY_CORE1_CLKGATE_CTRL, 0x55555555, 0, 32},
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{DOLBY_CORE2A_CLKGATE_CTRL, 0x55555555, 0, 32},
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{DOLBY_CORE3_CLKGATE_CTRL, 0x55555555, 0, 32},
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{VPU_REG_END, 0, 0, 0},
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};
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static struct vpu_ctrl_s vpu_module_init_tm2[] = {
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/* reg, val, bit, len */
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{DOLBY_CORE1_CLKGATE_CTRL, 0x55555555, 0, 32},
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{DOLBY_CORE2A_CLKGATE_CTRL, 0x55555555, 0, 32},
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{DOLBY_CORE3_CLKGATE_CTRL, 0x55555555, 0, 32},
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{DOLBY_CORE1_1_CLKGATE_CTRL,0x55555555, 0, 32},
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{DOLBY_TM2_TV_CLKGATE_CTRL, 0x55555555, 0, 32},
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{VPU_REG_END, 0, 0, 0},
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};
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/* ******************************************************* */
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/* VPU reset table */
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/* ******************************************************* */
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static struct vpu_reset_s vpu_reset_gx[] = {
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/* reg, mask */
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{RESET0_LEVEL, ((1<<5) | (1<<10) | (1<<19) | (1<<13))},
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{RESET1_LEVEL, (1<<5)},
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{RESET2_LEVEL, (1<<15)},
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{RESET4_LEVEL, ((1<<6) | (1<<7) | (1<<13) | (1<<5) | (1<<9) | (1<<4) | (1<<12))},
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{RESET7_LEVEL, (1<<7)},
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{VPU_REG_END, 0},
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};
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static struct vpu_reset_s vpu_reset_txhd[] = {
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/* reg, mask */
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{RESET0_LEVEL, ((1<<5) | (1<<10) | (1<<19) | (1<<13))},
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{RESET1_LEVEL, (1<<5)},
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{RESET2_LEVEL, (1<<15)},
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{RESET4_LEVEL, ((1<<6) | (1<<7) | (1<<13) | (1<<5) | (1<<9) | (1<<4) | (1<<12))},
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{RESET7_LEVEL, ((1<<7) | (1<<12))}, /* bit[12]:tcon */
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{VPU_REG_END, 0},
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};
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static struct vpu_reset_s vpu_reset_tl1[] = {
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/* reg, mask */
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{RESET0_LEVEL, ((1<<5) | (1<<10) | (1<<19) | (1<<13))},
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{RESET1_LEVEL, ((1<<5) | (1<<4))},
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{RESET2_LEVEL, (1<<15)},
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{RESET4_LEVEL, ((1<<6) | (1<<7) | (1<<13) | (1<<5) | (1<<9) | (1<<4) | (1<<12))},
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{RESET7_LEVEL, (1<<7)},
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{VPU_REG_END, 0},
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};
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#endif
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