529 lines
19 KiB
C
529 lines
19 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* drivers/vpp/aml_vpp_reg.h
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*
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* Copyright (C) 2020 Amlogic, Inc. All rights reserved.
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*
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*/
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#ifndef __VPP_REG_H__
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#define __VPP_REG_H__
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#include <asm/arch/io.h>
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#include <asm/arch/secure_apb.h>
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#ifdef CONFIG_AML_VPU_REG_NEW
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#include <asm/arch/vpu_regs.h>
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#endif
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/* ********************************
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* register define
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* ********************************* */
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/* base & offset */
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//#define REG_BASE_VCBUS (0xd0100000L)
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#define REG_OFFSET_VCBUS(reg) ((reg) << 2)
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/* memory mapping */
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#define REG_ADDR_VCBUS(reg) (reg & REG_BASE_VCBUS ? reg + 0L : REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg))
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#ifdef VPP_EOTF_CTL
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#define VIU_EOTF_CTL VPP_EOTF_CTL
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#endif
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#ifdef VPP_EOTF_LUT_ADDR_PORT
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#define VIU_EOTF_LUT_ADDR_PORT VPP_EOTF_LUT_ADDR_PORT
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#endif
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#ifdef VPP_EOTF_LUT_DATA_PORT
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#define VIU_EOTF_LUT_DATA_PORT VPP_EOTF_LUT_DATA_PORT
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#endif
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/* ********************************
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* dummy registers *
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* ********************************* */
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#ifndef VPP_POST2_MATRIX_PRE_OFFSET0_1
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#define VPP_POST2_MATRIX_PRE_OFFSET0_1 0x39ab
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#endif
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#ifndef VPP_POST2_MATRIX_PRE_OFFSET2
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#define VPP_POST2_MATRIX_PRE_OFFSET2 0x39ac
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#endif
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#ifndef VPP_POST2_MATRIX_COEF00_01
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#define VPP_POST2_MATRIX_COEF00_01 0x39a0
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#endif
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#ifndef VPP_POST2_MATRIX_COEF02_10
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#define VPP_POST2_MATRIX_COEF02_10 0x39a1
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#endif
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#ifndef VPP_POST2_MATRIX_COEF11_12
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#define VPP_POST2_MATRIX_COEF11_12 0x39a2
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#endif
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#ifndef VPP_POST2_MATRIX_COEF20_21
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#define VPP_POST2_MATRIX_COEF20_21 0x39a3
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#endif
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#ifndef VPP_POST2_MATRIX_COEF22
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#define VPP_POST2_MATRIX_COEF22 0x39a4
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#endif
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#ifndef VPP_POST2_MATRIX_OFFSET0_1
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#define VPP_POST2_MATRIX_OFFSET0_1 0x39a9
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#endif
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#ifndef VPP_POST2_MATRIX_OFFSET2
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#define VPP_POST2_MATRIX_OFFSET2 0x39aa
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#endif
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#ifndef VPP_POST2_MATRIX_EN_CTRL
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#define VPP_POST2_MATRIX_EN_CTRL 0x39ad
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#endif
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#ifndef VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1
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#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 0x3d6b
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#endif
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#ifndef VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2
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#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 0x3d6c
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#endif
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#ifndef VPP_WRAP_OSD1_MATRIX_COEF00_01
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#define VPP_WRAP_OSD1_MATRIX_COEF00_01 0x3d60
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#endif
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#ifndef VPP_WRAP_OSD1_MATRIX_COEF02_10
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#define VPP_WRAP_OSD1_MATRIX_COEF02_10 0x3d61
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#endif
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#ifndef VPP_WRAP_OSD1_MATRIX_COEF11_12
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#define VPP_WRAP_OSD1_MATRIX_COEF11_12 0x3d62
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#endif
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#ifndef VPP_WRAP_OSD1_MATRIX_COEF20_21
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#define VPP_WRAP_OSD1_MATRIX_COEF20_21 0x3d63
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#endif
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#ifndef VPP_WRAP_OSD1_MATRIX_COEF22
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#define VPP_WRAP_OSD1_MATRIX_COEF22 0x3d64
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#endif
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#ifndef VPP_WRAP_OSD1_MATRIX_OFFSET0_1
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#define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 0x3d69
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#endif
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#ifndef VPP_WRAP_OSD1_MATRIX_OFFSET2
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#define VPP_WRAP_OSD1_MATRIX_OFFSET2 0x3d6a
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#endif
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#ifndef VPP_WRAP_OSD1_MATRIX_EN_CTRL
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#define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d
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#endif
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#ifndef VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1
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#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 0x3d7b
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#endif
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#ifndef VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2
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#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 0x3d7c
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#endif
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#ifndef VPP_WRAP_OSD2_MATRIX_COEF00_01
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#define VPP_WRAP_OSD2_MATRIX_COEF00_01 0x3d70
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#endif
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#ifndef VPP_WRAP_OSD2_MATRIX_COEF02_10
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#define VPP_WRAP_OSD2_MATRIX_COEF02_10 0x3d71
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#endif
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#ifndef VPP_WRAP_OSD2_MATRIX_COEF11_12
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#define VPP_WRAP_OSD2_MATRIX_COEF11_12 0x3d72
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#endif
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#ifndef VPP_WRAP_OSD2_MATRIX_COEF20_21
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#define VPP_WRAP_OSD2_MATRIX_COEF20_21 0x3d73
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#endif
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#ifndef VPP_WRAP_OSD2_MATRIX_COEF22
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#define VPP_WRAP_OSD2_MATRIX_COEF22 0x3d74
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#endif
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#ifndef VPP_WRAP_OSD2_MATRIX_OFFSET0_1
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#define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 0x3d79
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#endif
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#ifndef VPP_WRAP_OSD2_MATRIX_OFFSET2
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#define VPP_WRAP_OSD2_MATRIX_OFFSET2 0x3d7a
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#endif
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#ifndef VPP_WRAP_OSD2_MATRIX_EN_CTRL
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#define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d
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#endif
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#ifndef VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1
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#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 0x3dbb
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#endif
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#ifndef VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2
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#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc
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#endif
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#ifndef VPP_WRAP_OSD3_MATRIX_COEF00_01
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#define VPP_WRAP_OSD3_MATRIX_COEF00_01 0x3db0
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#endif
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#ifndef VPP_WRAP_OSD3_MATRIX_COEF02_10
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#define VPP_WRAP_OSD3_MATRIX_COEF02_10 0x3db1
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#endif
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#ifndef VPP_WRAP_OSD3_MATRIX_COEF11_12
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#define VPP_WRAP_OSD3_MATRIX_COEF11_12 0x3db2
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#endif
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#ifndef VPP_WRAP_OSD3_MATRIX_COEF20_21
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#define VPP_WRAP_OSD3_MATRIX_COEF20_21 0x3db3
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#endif
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#ifndef VPP_WRAP_OSD3_MATRIX_COEF22
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#define VPP_WRAP_OSD3_MATRIX_COEF22 0x3db4
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#endif
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#ifndef VPP_WRAP_OSD3_MATRIX_OFFSET0_1
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#define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 0x3db9
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#endif
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#ifndef VPP_WRAP_OSD3_MATRIX_OFFSET2
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#define VPP_WRAP_OSD3_MATRIX_OFFSET2 0x3dba
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#endif
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#ifndef VPP_WRAP_OSD3_MATRIX_EN_CTRL
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#define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd
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#endif
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#ifndef VPU_VENCX_CLK_CTRL
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#define VPU_VENCX_CLK_CTRL 0x2785
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#endif
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#ifndef DOLBY_PATH_CTRL
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#define DOLBY_PATH_CTRL 0x1a0c
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#endif
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/*hdr2 register*/
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#define VD1_HDR2_CTRL 0x3800
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#define VD1_HDR2_CLK_GATE 0x3801
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#define VD1_HDR2_MATRIXI_COEF00_01 0x3802
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#define VD1_HDR2_MATRIXI_COEF02_10 0x3803
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#define VD1_HDR2_MATRIXI_COEF11_12 0x3804
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#define VD1_HDR2_MATRIXI_COEF20_21 0x3805
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#define VD1_HDR2_MATRIXI_COEF22 0x3806
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#define VD1_HDR2_MATRIXI_COEF30_31 0x3807
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#define VD1_HDR2_MATRIXI_COEF32_40 0x3808
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#define VD1_HDR2_MATRIXI_COEF41_42 0x3809
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#define VD1_HDR2_MATRIXI_OFFSET0_1 0x380a
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#define VD1_HDR2_MATRIXI_OFFSET2 0x380b
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#define VD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x380c
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#define VD1_HDR2_MATRIXI_PRE_OFFSET2 0x380d
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#define VD1_HDR2_MATRIXO_COEF00_01 0x380e
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#define VD1_HDR2_MATRIXO_COEF02_10 0x380f
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#define VD1_HDR2_MATRIXO_COEF11_12 0x3810
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#define VD1_HDR2_MATRIXO_COEF20_21 0x3811
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#define VD1_HDR2_MATRIXO_COEF22 0x3812
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#define VD1_HDR2_MATRIXO_COEF30_31 0x3813
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#define VD1_HDR2_MATRIXO_COEF32_40 0x3814
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#define VD1_HDR2_MATRIXO_COEF41_42 0x3815
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#define VD1_HDR2_MATRIXO_OFFSET0_1 0x3816
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#define VD1_HDR2_MATRIXO_OFFSET2 0x3817
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#define VD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x3818
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#define VD1_HDR2_MATRIXO_PRE_OFFSET2 0x3819
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#define VD1_HDR2_MATRIXI_CLIP 0x381a
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#define VD1_HDR2_MATRIXO_CLIP 0x381b
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#define VD1_HDR2_CGAIN_OFFT 0x381c
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#define VD1_EOTF_LUT_ADDR_PORT 0x381e
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#define VD1_EOTF_LUT_DATA_PORT 0x381f
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#define VD1_OETF_LUT_ADDR_PORT 0x3820
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#define VD1_OETF_LUT_DATA_PORT 0x3821
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#define VD1_CGAIN_LUT_ADDR_PORT 0x3822
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#define VD1_CGAIN_LUT_DATA_PORT 0x3823
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#define VD1_HDR2_CGAIN_COEF0 0x3824
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#define VD1_HDR2_CGAIN_COEF1 0x3825
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#define VD1_OGAIN_LUT_ADDR_PORT 0x3826
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#define VD1_OGAIN_LUT_DATA_PORT 0x3827
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#define VD1_HDR2_ADPS_CTRL 0x3828
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#define VD1_HDR2_ADPS_ALPHA0 0x3829
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#define VD1_HDR2_ADPS_ALPHA1 0x382a
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#define VD1_HDR2_ADPS_BETA0 0x382b
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#define VD1_HDR2_ADPS_BETA1 0x382c
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#define VD1_HDR2_ADPS_BETA2 0x382d
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#define VD1_HDR2_ADPS_COEF0 0x382e
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#define VD1_HDR2_ADPS_COEF1 0x382f
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#define VD1_HDR2_GMUT_CTRL 0x3830
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#define VD1_HDR2_GMUT_COEF0 0x3831
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#define VD1_HDR2_GMUT_COEF1 0x3832
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#define VD1_HDR2_GMUT_COEF2 0x3833
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#define VD1_HDR2_GMUT_COEF3 0x3834
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#define VD1_HDR2_GMUT_COEF4 0x3835
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#define VD1_HDR2_PIPE_CTRL1 0x3836
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#define VD1_HDR2_PIPE_CTRL2 0x3837
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#define VD1_HDR2_PIPE_CTRL3 0x3838
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#define VD1_HDR2_PROC_WIN1 0x3839
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#define VD1_HDR2_PROC_WIN2 0x383a
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#define VD1_HDR2_MATRIXI_EN_CTRL 0x383b
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#define VD1_HDR2_MATRIXO_EN_CTRL 0x383c
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#define VD2_HDR2_CTRL 0x3850
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#define VD2_HDR2_CLK_GATE 0x3851
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#define VD2_HDR2_MATRIXI_COEF00_01 0x3852
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#define VD2_HDR2_MATRIXI_COEF02_10 0x3853
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#define VD2_HDR2_MATRIXI_COEF11_12 0x3854
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#define VD2_HDR2_MATRIXI_COEF20_21 0x3855
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#define VD2_HDR2_MATRIXI_COEF22 0x3856
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#define VD2_HDR2_MATRIXI_COEF30_31 0x3857
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#define VD2_HDR2_MATRIXI_COEF32_40 0x3858
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#define VD2_HDR2_MATRIXI_COEF41_42 0x3859
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#define VD2_HDR2_MATRIXI_OFFSET0_1 0x385a
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#define VD2_HDR2_MATRIXI_OFFSET2 0x385b
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#define VD2_HDR2_MATRIXI_PRE_OFFSET0_1 0x385c
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#define VD2_HDR2_MATRIXI_PRE_OFFSET2 0x385d
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#define VD2_HDR2_MATRIXO_COEF00_01 0x385e
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#define VD2_HDR2_MATRIXO_COEF02_10 0x385f
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#define VD2_HDR2_MATRIXO_COEF11_12 0x3860
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#define VD2_HDR2_MATRIXO_COEF20_21 0x3861
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#define VD2_HDR2_MATRIXO_COEF22 0x3862
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#define VD2_HDR2_MATRIXO_COEF30_31 0x3863
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#define VD2_HDR2_MATRIXO_COEF32_40 0x3864
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#define VD2_HDR2_MATRIXO_COEF41_42 0x3865
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#define VD2_HDR2_MATRIXO_OFFSET0_1 0x3866
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#define VD2_HDR2_MATRIXO_OFFSET2 0x3867
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#define VD2_HDR2_MATRIXO_PRE_OFFSET0_1 0x3868
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#define VD2_HDR2_MATRIXO_PRE_OFFSET2 0x3869
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#define VD2_HDR2_MATRIXI_CLIP 0x386a
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#define VD2_HDR2_MATRIXO_CLIP 0x386b
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#define VD2_HDR2_CGAIN_OFFT 0x386c
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#define VD2_EOTF_LUT_ADDR_PORT 0x386e
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#define VD2_EOTF_LUT_DATA_PORT 0x386f
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#define VD2_OETF_LUT_ADDR_PORT 0x3870
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#define VD2_OETF_LUT_DATA_PORT 0x3871
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#define VD2_CGAIN_LUT_ADDR_PORT 0x3872
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#define VD2_CGAIN_LUT_DATA_PORT 0x3873
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#define VD2_HDR2_CGAIN_COEF0 0x3874
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#define VD2_HDR2_CGAIN_COEF1 0x3875
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#define VD2_OGAIN_LUT_ADDR_PORT 0x3876
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#define VD2_OGAIN_LUT_DATA_PORT 0x3877
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#define VD2_HDR2_ADPS_CTRL 0x3878
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#define VD2_HDR2_ADPS_ALPHA0 0x3879
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#define VD2_HDR2_ADPS_ALPHA1 0x387a
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#define VD2_HDR2_ADPS_BETA0 0x387b
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#define VD2_HDR2_ADPS_BETA1 0x387c
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#define VD2_HDR2_ADPS_BETA2 0x387d
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#define VD2_HDR2_ADPS_COEF0 0x387e
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#define VD2_HDR2_ADPS_COEF1 0x387f
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#define VD2_HDR2_GMUT_CTRL 0x3880
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#define VD2_HDR2_GMUT_COEF0 0x3881
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#define VD2_HDR2_GMUT_COEF1 0x3882
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#define VD2_HDR2_GMUT_COEF2 0x3883
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#define VD2_HDR2_GMUT_COEF3 0x3884
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#define VD2_HDR2_GMUT_COEF4 0x3885
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#define VD2_HDR2_PIPE_CTRL1 0x3886
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#define VD2_HDR2_PIPE_CTRL2 0x3887
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#define VD2_HDR2_PIPE_CTRL3 0x3888
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#define VD2_HDR2_PROC_WIN1 0x3889
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#define VD2_HDR2_PROC_WIN2 0x388a
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#define VD2_HDR2_MATRIXI_EN_CTRL 0x388b
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#define VD2_HDR2_MATRIXO_EN_CTRL 0x388c
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#define OSD1_HDR2_CTRL 0x38a0
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#define OSD1_HDR2_CLK_GATE 0x38a1
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#define OSD1_HDR2_MATRIXI_COEF00_01 0x38a2
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#define OSD1_HDR2_MATRIXI_COEF02_10 0x38a3
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#define OSD1_HDR2_MATRIXI_COEF11_12 0x38a4
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#define OSD1_HDR2_MATRIXI_COEF20_21 0x38a5
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#define OSD1_HDR2_MATRIXI_COEF22 0x38a6
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#define OSD1_HDR2_MATRIXI_COEF30_31 0x38a7
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#define OSD1_HDR2_MATRIXI_COEF32_40 0x38a8
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#define OSD1_HDR2_MATRIXI_COEF41_42 0x38a9
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#define OSD1_HDR2_MATRIXI_OFFSET0_1 0x38aa
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#define OSD1_HDR2_MATRIXI_OFFSET2 0x38ab
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#define OSD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x38ac
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#define OSD1_HDR2_MATRIXI_PRE_OFFSET2 0x38ad
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#define OSD1_HDR2_MATRIXO_COEF00_01 0x38ae
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#define OSD1_HDR2_MATRIXO_COEF02_10 0x38af
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#define OSD1_HDR2_MATRIXO_COEF11_12 0x38b0
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#define OSD1_HDR2_MATRIXO_COEF20_21 0x38b1
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#define OSD1_HDR2_MATRIXO_COEF22 0x38b2
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#define OSD1_HDR2_MATRIXO_COEF30_31 0x38b3
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#define OSD1_HDR2_MATRIXO_COEF32_40 0x38b4
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#define OSD1_HDR2_MATRIXO_COEF41_42 0x38b5
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#define OSD1_HDR2_MATRIXO_OFFSET0_1 0x38b6
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#define OSD1_HDR2_MATRIXO_OFFSET2 0x38b7
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#define OSD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x38b8
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#define OSD1_HDR2_MATRIXO_PRE_OFFSET2 0x38b9
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#define OSD1_HDR2_MATRIXI_CLIP 0x38ba
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#define OSD1_HDR2_MATRIXO_CLIP 0x38bb
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#define OSD1_HDR2_CGAIN_OFFT 0x38bc
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#define OSD1_EOTF_LUT_ADDR_PORT 0x38be
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#define OSD1_EOTF_LUT_DATA_PORT 0x38bf
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#define OSD1_OETF_LUT_ADDR_PORT 0x38c0
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#define OSD1_OETF_LUT_DATA_PORT 0x38c1
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#define OSD1_CGAIN_LUT_ADDR_PORT 0x38c2
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#define OSD1_CGAIN_LUT_DATA_PORT 0x38c3
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#define OSD1_HDR2_CGAIN_COEF0 0x38c4
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#define OSD1_HDR2_CGAIN_COEF1 0x38c5
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#define OSD1_OGAIN_LUT_ADDR_PORT 0x38c6
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#define OSD1_OGAIN_LUT_DATA_PORT 0x38c7
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#define OSD1_HDR2_ADPS_CTRL 0x38c8
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#define OSD1_HDR2_ADPS_ALPHA0 0x38c9
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#define OSD1_HDR2_ADPS_ALPHA1 0x38ca
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#define OSD1_HDR2_ADPS_BETA0 0x38cb
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#define OSD1_HDR2_ADPS_BETA1 0x38cc
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#define OSD1_HDR2_ADPS_BETA2 0x38cd
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#define OSD1_HDR2_ADPS_COEF0 0x38ce
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#define OSD1_HDR2_ADPS_COEF1 0x38cf
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#define OSD1_HDR2_GMUT_CTRL 0x38d0
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#define OSD1_HDR2_GMUT_COEF0 0x38d1
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#define OSD1_HDR2_GMUT_COEF1 0x38d2
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#define OSD1_HDR2_GMUT_COEF2 0x38d3
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#define OSD1_HDR2_GMUT_COEF3 0x38d4
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#define OSD1_HDR2_GMUT_COEF4 0x38d5
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#define OSD1_HDR2_PIPE_CTRL1 0x38d6
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#define OSD1_HDR2_PIPE_CTRL2 0x38d7
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#define OSD1_HDR2_PIPE_CTRL3 0x38d8
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#define OSD1_HDR2_PROC_WIN1 0x38d9
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#define OSD1_HDR2_PROC_WIN2 0x38da
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#define OSD1_HDR2_MATRIXI_EN_CTRL 0x38db
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#define OSD1_HDR2_MATRIXO_EN_CTRL 0x38dc
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#ifndef VIU2_OSD1_MATRIX_COEF00_01
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#define VIU2_OSD1_MATRIX_COEF00_01 0x1e70
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#endif
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#ifndef VIU2_OSD1_MATRIX_COEF02_10
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#define VIU2_OSD1_MATRIX_COEF02_10 0x1e71
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#endif
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#ifndef VIU2_OSD1_MATRIX_COEF11_12
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#define VIU2_OSD1_MATRIX_COEF11_12 0x1e72
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#endif
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#ifndef VIU2_OSD1_MATRIX_COEF20_21
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#define VIU2_OSD1_MATRIX_COEF20_21 0x1e73
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#endif
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#ifndef VIU2_OSD1_MATRIX_COEF22
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#define VIU2_OSD1_MATRIX_COEF22 0x1e74
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#endif
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#ifndef VIU2_OSD1_MATRIX_COEF13_14
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#define VIU2_OSD1_MATRIX_COEF13_14 0x1e75
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#endif
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#ifndef VIU2_OSD1_MATRIX_COEF23_24
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#define VIU2_OSD1_MATRIX_COEF23_24 0x1e76
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#endif
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#ifndef VIU2_OSD1_MATRIX_COEF15_25
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#define VIU2_OSD1_MATRIX_COEF15_25 0x1e77
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#endif
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#ifndef VIU2_OSD1_MATRIX_CLIP
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#define VIU2_OSD1_MATRIX_CLIP 0x1e78
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#endif
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#ifndef VIU2_OSD1_MATRIX_OFFSET0_1
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#define VIU2_OSD1_MATRIX_OFFSET0_1 0x1e79
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#endif
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#ifndef VIU2_OSD1_MATRIX_OFFSET2
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#define VIU2_OSD1_MATRIX_OFFSET2 0x1e7a
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#endif
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#ifndef VIU2_OSD1_MATRIX_PRE_OFFSET0_1
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#define VIU2_OSD1_MATRIX_PRE_OFFSET0_1 0x1e7b
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#endif
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#ifndef VIU2_OSD1_MATRIX_PRE_OFFSET2
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#define VIU2_OSD1_MATRIX_PRE_OFFSET2 0x1e7c
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#endif
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#ifndef VIU2_OSD1_MATRIX_EN_CTRL
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#define VIU2_OSD1_MATRIX_EN_CTRL 0x1e7d
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#endif
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#ifndef VPP_CLIP_MISC0
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#define VPP_CLIP_MISC0 0x1dd9
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#endif
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#ifndef VPP_CLIP_MISC1
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#define VPP_CLIP_MISC1 0x1dda
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#endif
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#define VPP_OSD1_MATRIX_COEF00_01 0x3910
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#define VPP_OSD1_MATRIX_COEF02_10 0x3911
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#define VPP_OSD1_MATRIX_COEF11_12 0x3912
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#define VPP_OSD1_MATRIX_COEF20_21 0x3913
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#define VPP_OSD1_MATRIX_COEF22 0x3914
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#define VPP_OSD1_MATRIX_COEF13_14 0x3915
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#define VPP_OSD1_MATRIX_COEF23_24 0x3916
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#define VPP_OSD1_MATRIX_COEF15_25 0x3917
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#define VPP_OSD1_MATRIX_CLIP 0x3918
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#define VPP_OSD1_MATRIX_OFFSET0_1 0x3919
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#define VPP_OSD1_MATRIX_OFFSET2 0x391a
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#define VPP_OSD1_MATRIX_PRE_OFFSET0_1 0x391b
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#define VPP_OSD1_MATRIX_PRE_OFFSET2 0x391c
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#define VPP_OSD1_MATRIX_EN_CTRL 0x391d
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#define VPP_OSD2_MATRIX_COEF00_01 0x3920
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#define VPP_OSD2_MATRIX_COEF02_10 0x3921
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#define VPP_OSD2_MATRIX_COEF11_12 0x3922
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#define VPP_OSD2_MATRIX_COEF20_21 0x3923
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#define VPP_OSD2_MATRIX_COEF22 0x3924
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#define VPP_OSD2_MATRIX_COEF13_14 0x3925
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#define VPP_OSD2_MATRIX_COEF23_24 0x3926
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#define VPP_OSD2_MATRIX_COEF15_25 0x3927
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#define VPP_OSD2_MATRIX_CLIP 0x3928
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#define VPP_OSD2_MATRIX_OFFSET0_1 0x3929
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#define VPP_OSD2_MATRIX_OFFSET2 0x392a
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#define VPP_OSD2_MATRIX_PRE_OFFSET0_1 0x392b
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#define VPP_OSD2_MATRIX_PRE_OFFSET2 0x392c
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#define VPP_OSD2_MATRIX_EN_CTRL 0x392d
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/*hdr2 register end*/
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#define LCD_GAMMA_CNTL_PORT0 0x14b4
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#define LCD_GAMMA_DATA_PORT0 0x14b5
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#define LCD_GAMMA_ADDR_PORT0 0x14b6
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//#define GAMMA_CNTL_PORT 0x1400
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#define GAMMA_VCOM_POL 7 /* RW */
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#define GAMMA_RVS_OUT 6 /* RW */
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#define ADR_RDY 5 /* Read Only */
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#define WR_RDY 4 /* Read Only */
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#define RD_RDY 3 /* Read Only */
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#define GAMMA_TR 2 /* RW */
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#define GAMMA_SET 1 /* RW */
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#define GAMMA_EN 0 /* RW */
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//#define GAMMA_DATA_PORT 0x1401
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//#define GAMMA_ADDR_PORT 0x1402
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#define H_RD 12
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#define H_AUTO_INC 11
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#define H_SEL_R 10
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#define H_SEL_G 9
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#define H_SEL_B 8
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#define HADR_MSB 7 /* 7:0 */
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#define HADR 0 /* 7:0 */
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/* ********************************
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* register access api
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* ********************************* */
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static inline unsigned int vpp_reg_read(unsigned int _reg)
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{
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return (*(volatile unsigned int *)REG_ADDR_VCBUS(_reg));
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};
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static inline void vpp_reg_write(unsigned int _reg, unsigned int _value)
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{
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*(volatile unsigned int *)REG_ADDR_VCBUS(_reg) = (_value);
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};
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static inline void vpp_reg_setb(unsigned int _reg, unsigned int _value,
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unsigned int _start, unsigned int _len)
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{
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vpp_reg_write(_reg, ((vpp_reg_read(_reg) &
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~(((1L << (_len))-1) << (_start))) |
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(((_value)&((1L<<(_len))-1)) << (_start))));
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}
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static inline unsigned int vpp_reg_getb(unsigned int _reg,
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unsigned int _start, unsigned int _len)
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{
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return (vpp_reg_read(_reg) >> (_start)) & ((1L << (_len)) - 1);
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}
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#endif
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