155 lines
3.8 KiB
C
155 lines
3.8 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* drivers/display/osd/osd_io.h
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*
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* Copyright (C) 2020 Amlogic, Inc. All rights reserved.
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*
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*/
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#ifndef _OSD_IO_H_
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#define _OSD_IO_H_
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#include <asm/arch/io.h>
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#include <asm/arch/secure_apb.h>
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#define REG_INDEX_VCBUS(reg) (u32)((reg) & REG_BASE_VCBUS ? ((reg - REG_BASE_VCBUS) >> 2) : reg)
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#define REG_OFFSET_CBUS(reg) ((reg) << 2)
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#define REG_OFFSET_VCBUS(reg) ((reg) << 2)
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#define REG_ADDR_CBUS(reg) ((reg) & REG_BASE_CBUS ? reg + 0L : REG_BASE_CBUS + REG_OFFSET_CBUS(reg))
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#define REG_ADDR_VCBUS(reg) ((reg) & REG_BASE_VCBUS ? reg + 0L : REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg))
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#define REG_ADDR_HIU(reg) (reg + 0L)
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#ifndef VIU_OSD3_BLK1_CFG_W4
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#define VIU_OSD3_BLK1_CFG_W4 0x3d99
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#endif
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#ifndef VIU_OSD3_BLK2_CFG_W4
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#define VIU_OSD3_BLK2_CFG_W4 0x3d9a
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#endif
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#ifndef VIU_OSD3_CTRL_STAT
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#define VIU_OSD3_CTRL_STAT 0x3d80
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#endif
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#ifndef VIU_VD1_PATH_CTRL
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#define VIU_VD1_PATH_CTRL 0x1a73
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#endif
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#ifndef VIU_VD2_PATH_CTRL
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#define VIU_VD2_PATH_CTRL 0x1a74
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#endif
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#ifndef VIU_OSD1_PATH_CTRL
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#define VIU_OSD1_PATH_CTRL 0x1a76
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#endif
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#ifndef VIU_OSD2_PATH_CTRL
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#define VIU_OSD2_PATH_CTRL 0x1a77
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#endif
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#ifndef VIU_OSD3_PATH_CTRL
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#define VIU_OSD3_PATH_CTRL 0x1a78
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#endif
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#ifndef VPP1_BLD_CTRL
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#define VPP1_BLD_CTRL 0x5985
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#endif
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#ifndef VPP2_BLD_CTRL
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#define VPP2_BLD_CTRL 0x59c5
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#endif
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#ifndef VPP1_BLEND_BLEND_DUMMY_DATA
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#define VPP1_BLEND_BLEND_DUMMY_DATA 0x59a9
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#endif
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#ifndef VPP1_BLEND_DUMMY_ALPHA
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#define VPP1_BLEND_DUMMY_ALPHA 0x59aa
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#endif
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#ifndef VPP2_BLEND_BLEND_DUMMY_DATA
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#define VPP2_BLEND_BLEND_DUMMY_DATA 0x59e9
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#endif
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#ifndef VPP2_BLEND_DUMMY_ALPHA
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#define VPP2_BLEND_DUMMY_ALPHA 0x59ea
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#endif
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static inline unsigned int osd_hiu_read(unsigned int _reg)
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{
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unsigned int val = 0;
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val = *(volatile unsigned int *)(REG_ADDR_HIU(_reg));
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return val;
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};
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static inline void osd_hiu_write(unsigned int _reg, unsigned int _value)
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{
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*(volatile unsigned int *)REG_ADDR_HIU(_reg) = (_value);
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};
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static inline void osd_hiu_setb(unsigned int _reg, unsigned int _value,
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unsigned int _start, unsigned int _len)
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{
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osd_hiu_write(_reg, ((osd_hiu_read(_reg) &
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~(((1L << (_len))-1) << (_start))) |
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(((_value)&((1L<<(_len))-1)) << (_start))));
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}
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static inline u32 osd_cbus_read(u32 reg)
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{
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return (*(volatile unsigned int *)REG_ADDR_CBUS(reg));
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}
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static inline void osd_cbus_write(u32 reg,
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const u32 val)
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{
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*(volatile unsigned int *)REG_ADDR_CBUS(reg) = (val);
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}
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static inline u32 osd_reg_read(u32 reg)
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{
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return (*(volatile unsigned int *)REG_ADDR_VCBUS(reg));
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}
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static inline void osd_reg_write(u32 reg,
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const u32 val)
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{
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*(volatile unsigned int *)REG_ADDR_VCBUS(reg) = (val);
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}
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static inline void osd_reg_set_mask(u32 reg,
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const u32 mask)
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{
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osd_reg_write(reg, (osd_reg_read(reg) | (mask)));
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}
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static inline void osd_reg_clr_mask(u32 reg,
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const u32 mask)
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{
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osd_reg_write(reg, (osd_reg_read(reg) & (~(mask))));
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}
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static inline void osd_reg_set_bits(u32 reg,
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const u32 value,
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const u32 start,
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const u32 len)
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{
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osd_reg_write(reg, ((osd_reg_read(reg) &
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~(((1L << (len)) - 1) << (start))) |
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(((value) & ((1L << (len)) - 1)) << (start))));
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}
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#define VSYNCOSD_RD_MPEG_REG(reg) osd_reg_read(reg)
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#define VSYNCOSD_WR_MPEG_REG(reg, val) osd_reg_write(reg, val)
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#define VSYNCOSD_WR_MPEG_REG_BITS(reg, val, start, len) \
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osd_reg_set_bits(reg, val, start, len)
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#define VSYNCOSD_SET_MPEG_REG_MASK(reg, mask) osd_reg_set_mask(reg, mask)
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#define VSYNCOSD_CLR_MPEG_REG_MASK(reg, mask) osd_reg_clr_mask(reg, mask)
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#endif
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