136 lines
5.0 KiB
C
136 lines
5.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* drivers/display/osd/osd_hw.h
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*
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* Copyright (C) 2020 Amlogic, Inc. All rights reserved.
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*
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*/
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#ifndef _OSD_HW_H_
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#define _OSD_HW_H_
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#include "osd.h"
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#ifdef CONFIG_AML_VPU_REG_NEW
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#define REG_OFFSET (0x20 << 2)
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#else
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#define REG_OFFSET (0x20)
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#endif
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#define OSD_RELATIVE_BITS 0x33370
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extern void osd_init_hw(void);
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extern void osd_set_color_key_hw(u32 index, u32 bpp, u32 colorkey);
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extern void osd_srckey_enable_hw(u32 index, u8 enable);
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extern void osd_set_gbl_alpha_hw(u32 index, u32 gbl_alpha);
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extern u32 osd_get_gbl_alpha_hw(u32 index);
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extern int read_rdma_table(void);
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extern void osd_set_color_mode(u32 index,
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const struct color_bit_define_s *color);
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extern void osd_update_disp_axis_hw(
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u32 index,
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u32 display_h_start,
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u32 display_h_end,
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u32 display_v_start,
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u32 display_v_end,
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u32 xoffset,
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u32 yoffset,
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u32 mode_change);
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extern void osd_setup_hw(u32 index,
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u32 xoffset,
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u32 yoffset,
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u32 xres,
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u32 yres,
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u32 xres_virtual ,
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u32 yres_virtual,
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u32 disp_start_x,
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u32 disp_start_y,
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u32 disp_end_x,
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u32 disp_end_y,
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u32 fbmem,
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const struct color_bit_define_s *color);
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extern void osd_set_order_hw(u32 index, u32 order);
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extern void osd_get_order_hw(u32 index, u32 *order);
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extern void osd_set_free_scale_enable_hw(u32 index, u32 enable);
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extern void osd_get_free_scale_enable_hw(u32 index, u32 *free_scale_enable);
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extern void osd_set_free_scale_mode_hw(u32 index, u32 freescale_mode);
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extern void osd_get_free_scale_mode_hw(u32 index, u32 *freescale_mode);
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extern void osd_set_4k2k_fb_mode_hw(u32 fb_for_4k2k);
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extern void osd_get_free_scale_mode_hw(u32 index, u32 *freescale_mode);
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extern void osd_set_free_scale_width_hw(u32 index, u32 width);
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extern void osd_get_free_scale_width_hw(u32 index, u32 *free_scale_width);
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extern void osd_set_free_scale_height_hw(u32 index, u32 height);
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extern void osd_get_free_scale_height_hw(u32 index, u32 *free_scale_height);
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extern void osd_get_free_scale_axis_hw(u32 index, s32 *x0, s32 *y0, s32 *x1,
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s32 *y1);
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extern void osd_set_free_scale_axis_hw(u32 index, s32 x0, s32 y0, s32 x1,
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s32 y1);
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extern void osd_get_scale_axis_hw(u32 index, s32 *x0, s32 *y0, s32 *x1,
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s32 *y1);
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extern void osd_get_window_axis_hw(u32 index, s32 *x0, s32 *y0, s32 *x1,
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s32 *y1);
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extern void osd_set_window_axis_hw(u32 index, s32 x0, s32 y0, s32 x1, s32 y1);
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extern void osd_set_scale_axis_hw(u32 index, s32 x0, s32 y0, s32 x1, s32 y1);
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extern void osd_get_block_windows_hw(u32 index, u32 *windows);
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extern void osd_set_block_windows_hw(u32 index, u32 *windows);
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extern void osd_get_block_mode_hw(u32 index, u32 *mode);
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extern void osd_set_block_mode_hw(u32 index, u32 mode);
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extern void osd_enable_3d_mode_hw(u32 index, u32 enable);
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extern void osd_set_2x_scale_hw(u32 index, u16 h_scale_enable,
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u16 v_scale_enable);
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extern void osd_get_flush_rate_hw(u32 *break_rate);
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extern void osd_set_reverse_hw(u32 index, u32 reverse);
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extern void osd_get_reverse_hw(u32 index, u32 *reverse);
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extern void osd_set_rotate_on_hw(u32 index, u32 on_off);
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extern void osd_get_rotate_on_hw(u32 index, u32 *on_off);
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extern void osd_set_antiflicker_hw(u32 index, u32 vmode, u32 yres);
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extern void osd_get_antiflicker_hw(u32 index, u32 *on_off);
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extern void osd_set_update_state_hw(u32 index, u32 up_free);
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extern void osd_get_update_state_hw(u32 index, u32 *up_free);
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extern void osd_get_angle_hw(u32 index, u32 *angle);
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extern void osd_set_angle_hw(u32 index, u32 angle, u32 virtual_osd1_yres,
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u32 virtual_osd2_yres);
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extern void osd_get_clone_hw(u32 index, u32 *clone);
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extern void osd_set_clone_hw(u32 index, u32 clone);
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extern void osd_set_update_pan_hw(u32 index);
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extern void osd_set_rotate_angle_hw(u32 index, u32 angle);
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extern void osd_get_rotate_angle_hw(u32 index, u32 *angle);
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extern void osd_get_prot_canvas_hw(u32 index, s32 *x_start, s32 *y_start,
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s32 *x_end, s32 *y_end);
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extern void osd_set_prot_canvas_hw(u32 index, s32 x_start, s32 y_start,
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s32 x_end, s32 y_end);
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extern void osd_setpal_hw(u32 index, unsigned regno, unsigned red,
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unsigned green, unsigned blue, unsigned transp);
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extern void osd_enable_hw(u32 index, u32 enable);
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extern void osd_pan_display_hw(u32 index, unsigned int xoffset,
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unsigned int yoffset);
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extern void osd_get_hw_para(struct hw_para_s **para);
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extern void osd_update_blend(struct pandata_s *disp_data);
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extern void osd_hist_enable(u32 osd_index);
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extern int osd_get_hist_stat(u32 *hist_result);
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#ifdef CONFIG_AML_MESON_G12A
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extern void osd_init_hw_viu2(void);
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#endif
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/******* dummy registers *********/
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#ifndef OSDSR_HV_SIZEIN
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#define OSDSR_HV_SIZEIN 0x3130
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#endif
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#ifndef OSDSR_CTRL_MODE
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#define OSDSR_CTRL_MODE 0x3131
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#endif
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#ifndef OSDSR_UK_GRAD2DDIAG_LIMIT
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#define OSDSR_UK_GRAD2DDIAG_LIMIT 0x313c
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#endif
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#ifndef OSDSR_UK_GRAD2DADJA_LIMIT
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#define OSDSR_UK_GRAD2DADJA_LIMIT 0x313e
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#endif
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#ifndef OSDSR_UK_BST_GAIN
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#define OSDSR_UK_BST_GAIN 0x313f
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#endif
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#ifndef VPU_PROT1_Y_START_END
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#define VPU_PROT1_Y_START_END 0x2753
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#endif
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#endif
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