97 lines
1.9 KiB
C
97 lines
1.9 KiB
C
/*
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* Copyright (C) 2015 Hardkernel Co,. Ltd
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* Dongjin Kim <[email protected]>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/arch/eth_setup.h>
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#include <asm/arch/secure_apb.h>
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#if defined(CONFIG_AML_ETHERNET)
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extern int aml_eth_init(bd_t *bis);
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struct eth_board_socket* eth_board_setup(char *name)
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{
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struct eth_board_socket* new_board;
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new_board = (struct eth_board_socket*)
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malloc(sizeof(struct eth_board_socket));
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if (NULL == new_board)
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return NULL;
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if (name != NULL) {
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new_board->name = (char*)malloc(strlen(name));
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strncpy(new_board->name, name, strlen(name));
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} else {
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new_board->name = CONFIG_SYS_BOARD;
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}
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new_board->eth_pinmux_setup = NULL ;
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new_board->eth_clock_configure = NULL;
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new_board->eth_hw_reset = NULL;
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return new_board;
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}
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static void setup_net_chip(void)
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{
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eth_aml_reg0_t reg;
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/*
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* Set up ethernet clk need calibrate to configure
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*/
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setbits_le32(P_PERIPHS_PIN_MUX_6, 0x3fff);
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reg.d32 = 0;
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reg.b.phy_intf_sel = 1;
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reg.b.data_endian = 0;
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reg.b.desc_endian = 0;
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reg.b.rx_clk_rmii_invert = 0;
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reg.b.rgmii_tx_clk_src = 0;
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reg.b.rgmii_tx_clk_phase = 1;
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reg.b.rgmii_tx_clk_ratio = 4;
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reg.b.phy_ref_clk_enable = 1;
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reg.b.clk_rmii_i_invert = 0;
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reg.b.clk_en = 1;
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reg.b.adj_enable = 0;
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reg.b.adj_setup = 0;
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reg.b.adj_delay = 0;
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reg.b.adj_skew = 0;
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reg.b.cali_start = 0;
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reg.b.cali_rise = 0;
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reg.b.cali_sel = 0;
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reg.b.rgmii_rx_reuse = 0;
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reg.b.eth_urgent = 0;
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/* RGMII Mode */
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setbits_le32(P_PREG_ETH_REG0, reg.d32);
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setbits_le32(HHI_GCLK_MPEG1, 1 << 3);
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/*
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* Power on memory
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*/
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clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
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/*
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* Hardware reset ethernet phy : GPIOZ_14
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*/
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clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 14);
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clrbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
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udelay(100000);
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setbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
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}
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int board_eth_init(bd_t *bis)
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{
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setup_net_chip();
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udelay(1000);
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aml_eth_init(bis);
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return 0;
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}
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#endif
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