384 lines
11 KiB
C
384 lines
11 KiB
C
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/*
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*
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <asm/arch/timing.h>
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#include <asm/arch/ddr_define.h>
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/* DDR freq range */
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#define CONFIG_DDR_CLK_LOW 375
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#define CONFIG_DDR_CLK_HIGH 1500
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/* DON'T OVER THESE RANGE */
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#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
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#error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
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#endif
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/* CPU freq range */
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#define CONFIG_CPU_CLK_LOW 600
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#define CONFIG_CPU_CLK_HIGH 2000
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/* DON'T OVER THESE RANGE */
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#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
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#error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
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#endif
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#define DDR3_DRV_40OHM 0
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#define DDR3_DRV_34OHM 1
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#define DDR3_ODT_0OHM 0
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#define DDR3_ODT_60OHM 1
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#define DDR3_ODT_120OHM 2
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#define DDR3_ODT_40OHM 3
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#define DDR3_ODT_20OHM 4
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#define DDR3_ODT_30OHM 5
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#define CFG_DDR3_DRV DDR3_DRV_40OHM
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#define CFG_DDR3_ODT DDR3_ODT_120OHM
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/*
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* these parameters are corresponding to the pcb layout,
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* please don't enable this function unless these signals
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* has been measured by oscilloscope.
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*/
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#ifdef CONFIG_DDR_CMD_BDL_TUNE
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#define DDR_AC_LCDLR 0
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#define DDR_CK0_BDL 18
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#define DDR_RAS_BDL 18
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#define DDR_CAS_BDL 24
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#define DDR_WE_BDL 21
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#define DDR_BA0_BDL 16
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#define DDR_BA1_BDL 2
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#define DDR_BA2_BDL 13
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#define DDR_ACPDD_BDL 27
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#define DDR_CS0_BDL 27
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#define DDR_CS1_BDL 27
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#define DDR_ODT0_BDL 27
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#define DDR_ODT1_BDL 27
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#define DDR_CKE0_BDL 27
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#define DDR_CKE1_BDL 27
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#define DDR_A0_BDL 14
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#define DDR_A1_BDL 9
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#define DDR_A2_BDL 5
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#define DDR_A3_BDL 18
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#define DDR_A4_BDL 4
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#define DDR_A5_BDL 16
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#define DDR_A6_BDL 1
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#define DDR_A7_BDL 10
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#define DDR_A8_BDL 4
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#define DDR_A9_BDL 7
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#define DDR_A10_BDL 10
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#define DDR_A11_BDL 9
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#define DDR_A12_BDL 6
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#define DDR_A13_BDL 16
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#define DDR_A14_BDL 8
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#define DDR_A15_BDL 27
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#endif
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/* CAUTION!! */
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/*
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* For DDR3:
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* 7-7-7: CONFIG_DDR_CLK range 375~ 533
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* 9-9-9: CONFIG_DDR_CLK range 533~ 667
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* 11-11-11: CONFIG_DDR_CLK range 667~ 800
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* 12-12-12: CONFIG_DDR_CLK range 800~ 933
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* 13-13-13: CONFIG_DDR_CLK range 933~1066
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* 14-14-14: CONFIG_DDR_CLK range 1066~1200
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*/
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ddr_timing_t __ddr_timming[] = {
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//ddr3_7_7_7
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{
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.identifier = CONFIG_DDR_TIMMING_DDR3_7,
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.cfg_ddr_rtp = (6),
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.cfg_ddr_wtr = (7),
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.cfg_ddr_rp = (7),
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.cfg_ddr_rcd = (7),
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.cfg_ddr_ras = (20),
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.cfg_ddr_rrd = (6),
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.cfg_ddr_rc = (27),
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.cfg_ddr_mrd = (4),
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.cfg_ddr_mod = (12),
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.cfg_ddr_faw = (27),
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.cfg_ddr_rfc = (160),
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.cfg_ddr_wlmrd = (40),
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.cfg_ddr_wlo = (6),
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.cfg_ddr_xs = (512),
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.cfg_ddr_xp = (7),
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.cfg_ddr_cke = (4),
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.cfg_ddr_dllk = (512),
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.cfg_ddr_rtodt = (0),
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.cfg_ddr_rtw = (4),
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.cfg_ddr_refi = (78),
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.cfg_ddr_refi_mddr3 = (4),
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.cfg_ddr_cl = (7),
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.cfg_ddr_wr = (12),
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.cfg_ddr_cwl = (5),
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.cfg_ddr_al = (0),
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.cfg_ddr_exsr = (512),
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.cfg_ddr_dqs = (4),
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.cfg_ddr_cksre = (15),
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.cfg_ddr_cksrx = (15),
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.cfg_ddr_zqcs = (64),
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.cfg_ddr_zqcl = (512),
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.cfg_ddr_xpdll = (20),
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.cfg_ddr_zqcsi = (1000),
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},
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//ddr3_9_9_9
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{
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.identifier = CONFIG_DDR_TIMMING_DDR3_9,
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.cfg_ddr_rtp = (6),
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.cfg_ddr_wtr = (7),
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.cfg_ddr_rp = (9),
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.cfg_ddr_rcd = (9),
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.cfg_ddr_ras = (27),
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.cfg_ddr_rrd = (6),
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.cfg_ddr_rc = (33),
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.cfg_ddr_mrd = (4),
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.cfg_ddr_mod = (12),
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.cfg_ddr_faw = (30),
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.cfg_ddr_rfc = (196),
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.cfg_ddr_wlmrd = (40),
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.cfg_ddr_wlo = (6),
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.cfg_ddr_xs = (512),
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.cfg_ddr_xp = (7),
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.cfg_ddr_cke = (4),
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.cfg_ddr_dllk = (512),
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.cfg_ddr_rtodt = (0),
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.cfg_ddr_rtw = (6),
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.cfg_ddr_refi = (78),
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.cfg_ddr_refi_mddr3 = (4),
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.cfg_ddr_cl = (9),
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.cfg_ddr_wr = (12),
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.cfg_ddr_cwl = (7),
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.cfg_ddr_al = (0),
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.cfg_ddr_exsr = (512),
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.cfg_ddr_dqs = (23),
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.cfg_ddr_cksre = (15),
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.cfg_ddr_cksrx = (15),
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.cfg_ddr_zqcs = (64),
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.cfg_ddr_zqcl = (136),
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.cfg_ddr_xpdll = (20),
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.cfg_ddr_zqcsi = (1000),
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},
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//ddr3_11_11_11
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{
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.identifier = CONFIG_DDR_TIMMING_DDR3_11,
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.cfg_ddr_rtp = (7),
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.cfg_ddr_wtr = (7),
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.cfg_ddr_rp = (11),
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.cfg_ddr_rcd = (11),
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.cfg_ddr_ras = (35),
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.cfg_ddr_rrd = (7),
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.cfg_ddr_rc = (45),
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.cfg_ddr_mrd = (6),
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.cfg_ddr_mod = (4),
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.cfg_ddr_faw = (33),
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.cfg_ddr_rfc = (280),
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.cfg_ddr_wlmrd = (40),
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.cfg_ddr_wlo = (7),
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.cfg_ddr_xs = (512),
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.cfg_ddr_xp = (5),
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.cfg_ddr_cke = (4),
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.cfg_ddr_dllk = (512),
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.cfg_ddr_rtodt = (0),
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.cfg_ddr_rtw = (7),
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.cfg_ddr_refi = (78),
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.cfg_ddr_refi_mddr3 = (4),
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.cfg_ddr_cl = (11),
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.cfg_ddr_wr = (12),
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.cfg_ddr_cwl = (8),
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.cfg_ddr_al = (0),
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.cfg_ddr_exsr = (512),
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.cfg_ddr_dqs = (23),
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.cfg_ddr_cksre = (15),
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.cfg_ddr_cksrx = (15),
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.cfg_ddr_zqcs = (64),
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.cfg_ddr_zqcl = (136),
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.cfg_ddr_xpdll = (23),
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.cfg_ddr_zqcsi = (1000),
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},
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//ddr3_13_13_13
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{
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.identifier = CONFIG_DDR_TIMMING_DDR3_13,
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.cfg_ddr_rtp = (7),
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.cfg_ddr_wtr = (7),
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.cfg_ddr_rp = (13),
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.cfg_ddr_rcd = (13),
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.cfg_ddr_ras = (37),
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.cfg_ddr_rrd = (7),
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.cfg_ddr_rc = (52),
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.cfg_ddr_mrd = (6),
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.cfg_ddr_mod = (4),
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.cfg_ddr_faw = (33),
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.cfg_ddr_rfc = (280),
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.cfg_ddr_wlmrd = (40),
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.cfg_ddr_wlo = (7),
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.cfg_ddr_xs = (512),
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.cfg_ddr_xp = (7),
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.cfg_ddr_cke = (5),
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.cfg_ddr_dllk = (512),
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.cfg_ddr_rtodt = (0),
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.cfg_ddr_rtw = (7),
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.cfg_ddr_refi = (78),
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.cfg_ddr_refi_mddr3 = (4),
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.cfg_ddr_cl = (13),
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.cfg_ddr_wr = (16),
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.cfg_ddr_cwl = (9),
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.cfg_ddr_al = (0),
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.cfg_ddr_exsr = (512),
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.cfg_ddr_dqs = (23),
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.cfg_ddr_cksre = (15),
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.cfg_ddr_cksrx = (15),
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.cfg_ddr_zqcs = (64),
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.cfg_ddr_zqcl = (136),
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.cfg_ddr_xpdll = (23),
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.cfg_ddr_zqcsi = (1000),
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},
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{
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.identifier = CONFIG_DDR_TIMMING_DDR3_14,
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.cfg_ddr_rtp = (7),
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.cfg_ddr_wtr = (7),
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.cfg_ddr_rp = (14),
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.cfg_ddr_rcd = (14),
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.cfg_ddr_ras = (37),
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.cfg_ddr_rrd = (7),
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.cfg_ddr_rc = (52),
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.cfg_ddr_mrd = (6),
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.cfg_ddr_mod = (4),
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.cfg_ddr_faw = (33),
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.cfg_ddr_rfc = (280),
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.cfg_ddr_wlmrd = (40),
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.cfg_ddr_wlo = (7),
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.cfg_ddr_xs = (512),
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.cfg_ddr_xp = (7),
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.cfg_ddr_cke = (5),
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.cfg_ddr_dllk = (512),
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.cfg_ddr_rtodt = (0),
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.cfg_ddr_rtw = (7),
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.cfg_ddr_refi = (78),
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.cfg_ddr_refi_mddr3 = (4),
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.cfg_ddr_cl = (14),
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.cfg_ddr_wr = (16),
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.cfg_ddr_cwl = (10),
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.cfg_ddr_al = (0),
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.cfg_ddr_exsr = (512),
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.cfg_ddr_dqs = (23),
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.cfg_ddr_cksre = (15),
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.cfg_ddr_cksrx = (15),
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.cfg_ddr_zqcs = (64),
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.cfg_ddr_zqcl = (136),
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.cfg_ddr_xpdll = (23),
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.cfg_ddr_zqcsi = (1000),
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}
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};
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ddr_set_t __ddr_setting = {
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/* common and function defines */
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.ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
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.ddr_type = CONFIG_DDR_TYPE,
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.ddr_clk = CONFIG_DDR_CLK,
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.ddr_base_addr = CFG_DDR_BASE_ADDR,
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.ddr_start_offset = CFG_DDR_START_OFFSET,
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.ddr_timing_ind = 0,
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.ddr_size = CONFIG_DDR_SIZE,
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.ddr_pll_ctrl = (0),
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.ddr_dmc_ctrl = 0,
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.ddr0_addrmap = {0},
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.ddr1_addrmap = {0},
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.ddr_2t_mode = 1,
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.ddr_full_test = CONFIG_DDR_FULL_TEST,
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.ddr_size_detect = CONFIG_DDR_SIZE_AUTO_DETECT,
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.ddr_drv = CFG_DDR3_DRV,
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.ddr_odt = CFG_DDR3_ODT,
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/* pub defines */
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.t_pub_ptr = {
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[0] = ( 6 | (320 << 6) | (80 << 21)),
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[1] = (120 | (1000 << 16)),
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[2] = 0,
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[3] = (20000 | (136 << 20)),
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[4] = (1000 | (180 << 16)),
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}, //PUB PTR0-3
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.t_pub_odtcr = 0x00210000,
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.t_pub_mr = {0},
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.t_pub_dtpr = {0},
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.t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
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.t_pub_pgcr1 = 0x0380c6a0, //PUB PGCR1
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//.t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
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.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
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.t_pub_pgcr3 = 0xc0aafe60, //PUB PGCR3
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.t_pub_dxccr = 0x00181884, //PUB DXCCR
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.t_pub_dtcr = 0x43003087, //PUB DTCR
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.t_pub_aciocr = {0}, //PUB ACIOCRx
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.t_pub_dx0gcr = {0}, //PUB DX0GCRx
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.t_pub_dx1gcr = {0}, //PUB DX1GCRx
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.t_pub_dx2gcr = {0}, //PUB DX2GCRx
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.t_pub_dx3gcr = {0}, //PUB DX3GCRx
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.t_pub_dcr = 0XB, //PUB DCR
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.t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
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.t_pub_dsgcr = 0x020645a,
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//.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
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//.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
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//.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
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//.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
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.t_pub_zq0pr = 0x69, //PUB ZQ0PR
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.t_pub_zq1pr = 0x69, //PUB ZQ1PR
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.t_pub_zq2pr = 0x69, //PUB ZQ2PR
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.t_pub_zq3pr = 0x69, //PUB ZQ3PR
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/* pctl0 defines */
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/* pctl1 use same define as pctl0 */
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.t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
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.t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
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.t_pctl0_init_us = 2, //PCTL TINIT
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.t_pctl0_rsth_us = 2, //PCTL TRSTH
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.t_pctl0_mcfg = 0XA2F21, //PCTL MCFG default 1T
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//.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
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.t_pctl0_mcfg1 = (1<<31)|(0x20<<16)|(0x0<<0)//[B31]hw_exit_idle_en
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|( 0<<8), //[B10,B9,B8] tfaw_cfg_offset:
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//tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
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.t_pctl0_scfg = 0xF01, //PCTL SCFG
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.t_pctl0_sctl = 0x1, //PCTL SCTL
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//.t_pctl0_ppcfg = (0xF0 << 1),
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.t_pctl0_dfistcfg0 = 0x4,
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.t_pctl0_dfistcfg1 = 0x1,
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.t_pctl0_dfitctrldelay = 2,
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.t_pctl0_dfitphywrdata = 1,
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.t_pctl0_dfitphywrlta = 2,
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.t_pctl0_dfitrddataen = 3,
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.t_pctl0_dfitphyrdlat = 16,
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.t_pctl0_dfitdramclkdis = 1,
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.t_pctl0_dfitdramclken = 1,
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.t_pctl0_dfitphyupdtype1 = 0x200,
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.t_pctl0_dfitctrlupdmin = 16,
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.t_pctl0_cmdtstaten = 1,
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//.t_pctl0_dfiodtcfg = 8,
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//.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
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.t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
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.t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
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.t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (3 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
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.t_pub_acbdlr0 = 0x10, //2015.09.21 add for CK0 delay fine tune
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};
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pll_set_t __pll_setting = {
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.cpu_clk = CONFIG_CPU_CLK / 24 * 24,
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.spi_ctrl = 0,
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.vddee = CONFIG_VDDEE_INIT_VOLTAGE,
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.vcck = CONFIG_VCCK_INIT_VOLTAGE,
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.lCustomerID = CONFIG_AML_CUSTOMER_ID,
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};
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