127 lines
2.0 KiB
ArmAsm
127 lines
2.0 KiB
ArmAsm
// See LICENSE for license details.
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#include "riscv_encoding.h"
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#include "soc.h"
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.section .init
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.globl _start
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.type _start,@function
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_start:
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csrc CSR_MSTATUS, MSTATUS_MIE
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#ifndef N200_REVA
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/* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */
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li t0, (0x1 << 9);
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csrs CSR_MMISC_CTL, t0
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/* Initial the mtvt*/
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la t0, vector_base
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csrw CSR_MTVT, t0
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/* Initial the mtvt2 and enable it*/
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la t0, irq_entry
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csrw CSR_MTVT2, t0
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csrs CSR_MTVT2, 0x1
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/* Initial the CSR MTVEC for the Trap ane NMI base addr*/
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la t0, trap_entry
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li t1, 0x3 // use ucliec
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or t0, t0, t1
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csrw CSR_MTVEC, t0
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#ifdef MPU_INIT
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/* Setup MPU */
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li t0, SOC_PMP_BASE
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/* Enable SRAM full range rwx */
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li t1, SRAM_BEGIN
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li t2, SRAM_END - 0x80
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add t1, t1, 0x0f
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sw t2, 28(t0)
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sw t1, 24(t0)
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/* Enable IO full range rw */
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li t1, IO_BEGIN
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li t2, IO_END - 0x80
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add t1, t1, 0x0d
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sw t2, 20(t0)
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sw t1, 16(t0)
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#endif
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#ifdef __riscv_flen
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/* Enable FPU */
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li t0, MSTATUS_FS
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csrs mstatus, t0
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csrw fcsr, x0
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#endif
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#endif
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.option push
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.option norelax
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.option pop
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la sp, _sp
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#if defined (SOC_t3)
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/* Fixme T3 axi_ram access issue */
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lw a0, _data_start
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lw a1, _data_end
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lw a2, _data_img
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bgeu a0, a1, 2f
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1:
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lw a3, 0(a2)
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sw a3, (a0)
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addi a0, a0, 4
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addi a2, a2, 4
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bltu a0, a1, 1b
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2:
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#endif
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/* Clear bss section */
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lw a0, _bss_start
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lw a1, _bss_end
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bgeu a0, a1, 2f
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1:
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sw zero, (a0)
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addi a0, a0, 4
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bltu a0, a1, 1b
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2:
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/* argc = argv = 0 */
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li a0, 0
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li a1, 0
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call main
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1:
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j 1b
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_bss_end:
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.long _ebss
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_bss_start:
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.long _bss
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#if defined (SOC_t3)
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_data_end:
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.long _edata
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_data_start:
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.long _data
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_data_img:
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.long _data_img_start
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#endif
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#ifndef N200_REVA
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.global disable_mcycle_minstret
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disable_mcycle_minstret:
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csrsi CSR_MCOUNTINHIBIT, 0x5
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ret
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.global enable_mcycle_minstret
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enable_mcycle_minstret:
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csrci CSR_MCOUNTINHIBIT, 0x5
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ret
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.global core_wfe
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core_wfe:
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csrc CSR_MSTATUS, MSTATUS_MIE
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csrs CSR_WFE, 0x1
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wfi
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csrc CSR_WFE, 0x1
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csrs CSR_MSTATUS, MSTATUS_MIE
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ret
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#endif
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