33 lines
859 B
C
33 lines
859 B
C
/*
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* Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef __SOC_H
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#define __SOC_H
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#define SOC_PIC_NUM_INTERRUPTS 112
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#define SOC_PIC_CTRL_ADDR 0x03000000
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#define SOC_TIMER_CTRL_ADDR 0x02000000
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#define SOC_TIMER_FREQ 24000000
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#if (SOC_PIC_NUM_INTERRUPTS / 32) * 32 == SOC_PIC_NUM_INTERRUPTS
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#define IRQ_EN_REG_NUM (SOC_PIC_NUM_INTERRUPTS / 32)
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#else
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#define IRQ_EN_REG_NUM (SOC_PIC_NUM_INTERRUPTS / 32 + 1)
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#endif
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/*SoC/Shadow register mapping*/
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#define VRTC_PARA_REG AO_DEBUG_REG2
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#define VRTC_STICKY_REG AO_RTI_STICKY_REG2
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#define TIMERE_LOW_REG ISA_TIMERE
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#define TIMERE_HIG_REG ISA_TIMERE_HI
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#define WAKEUP_REASON_STICK_REG PREG_STICKY_REG3
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#define FSM_TRIGER_CTRL AO_TIMER_CTRL
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#define FSM_TRIGER_SRC AO_DEBUG_REG2 //Just for run happy. Need fix it!!!!
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#define UART_PORT_CONS UART1_WFIFO
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#endif
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