28 lines
532 B
C
28 lines
532 B
C
/*
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* Copyright (c) 2021-2023 Amlogic, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef _SARADC_DATA_H_
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#define _SARADC_DATA_H_
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#include <register.h>
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#define SAR_CLK_BASE CLKCTRL_SAR_CLK_CTRL0
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#define SARADC_BASE SAR_ADC_REG0
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#define REG11_VREF_EN_VALUE 1
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#define REG11_CMV_SEL_VALUE 1
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#define REG11_EOC_VALUE 0
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/* s1a saradc interrupt num */
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#define SARADC_INTERRUPT_NUM 181
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#define SARADC_REG_NUM (18 + 1)
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/* bandgap of gxlx3/txhd2/s1a is bit12 */
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#define SARADC_REG11_BANDGAP_EN_BIT 12
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#endif
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