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99 lines
2.0 KiB
C

/*
* Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved.
*
* SPDX-License-Identifier: MIT
*/
#include "riscv_pma.h"
#include "riscv_encoding.h"
/*
* set physical memory attribution for region
* idx: region num
* start_addr: 4k alignment
* mask: ~(size - 1), 4k alignment
* attr: 3: enable device, 5: enable noncacheable.
* bit2: Nocacheable region
* bit1: device region
* bit0: enable or disable
*/
void set_region_mem_attr(int idx, uint32_t start_addr, uint32_t mask, uint8_t attr)
{
start_addr = start_addr & ~0xfff;
mask = mask & ~0xfff;
attr = attr & 0xf;
switch (idx) {
case 0:
write_csr(mattri0_mask, mask);
write_csr(mattri0_base, start_addr | (attr<<0));
break;
case 1:
write_csr(mattri1_mask, mask);
write_csr(mattri1_base, start_addr | (attr<<0));
break;
case 2:
write_csr(mattri2_mask, mask);
write_csr(mattri2_base, start_addr | (attr<<0));
break;
case 3:
write_csr(mattri3_mask, mask);
write_csr(mattri3_base, start_addr | (attr<<0));
break;
case 4:
write_csr(mattri4_mask, mask);
write_csr(mattri4_base, start_addr | (attr<<0));
break;
case 5:
write_csr(mattri5_mask, mask);
write_csr(mattri5_base, start_addr | (attr<<0));
break;
case 6:
write_csr(mattri6_mask, mask);
write_csr(mattri6_base, start_addr | (attr<<0));
break;
case 7:
write_csr(mattri7_mask, mask);
write_csr(mattri7_base, start_addr | (attr<<0));
break;
default:
printf("Error: support 8 regions. Idx: %d\n", idx);
break;
}
}
// disable region attributions
void disable_region_attr(int idx)
{
switch (idx) {
case 0:
write_csr(mattri0_base, 0);
break;
case 1:
write_csr(mattri1_base, 0);
break;
case 2:
write_csr(mattri2_base, 0);
break;
case 3:
write_csr(mattri3_base, 0);
break;
case 4:
write_csr(mattri4_base, 0);
break;
case 5:
write_csr(mattri5_base, 0);
break;
case 6:
write_csr(mattri6_base, 0);
break;
case 7:
write_csr(mattri7_base, 0);
break;
default:
printf("Error: support 8 regions. Idx: %d\n", idx);
break;
};
}