41 lines
977 B
C
41 lines
977 B
C
/*
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* Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef _SARADC_DATA_H_
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#define _SARADC_DATA_H_
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#include <register.h>
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#include "irq.h"
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#define SAR_CLK_BASE CLKCTRL_SAR_CLK_CTRL0
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#define SARADC_BASE SAR_ADC_REG0
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#define SAR_SYS_CLK_EN_BASE CLKCTRL_SYS_CLK_EN0_REG2
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#define SAR_SYS_CLK_EN_BIT 28
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#define SARADC_APPLY_WORKAROUND
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#define SARADC_RESET_REG RESETCTRL_RESET2
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#define SARADC_RESET_DIGITAL_BIT 18
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#define SARADC_RESET_ANALOG_BUILDIN
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#define SARADC_RESET_ANALOG_REG SAR_ADC_REG4
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#define SARADC_RESET_ANALOG_BIT 25
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#define SARADC_RESET_ANALOG_ACTIVE 0
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#define SARADC_REG7_INIT 0x00000c11
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#define SARADC_REG8_INIT 0x0280614d
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#define SARADC_REG3_INIT 0x10a02403
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#define SARADC_REG4_INIT 0x021e5080
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#define SARADC_REG9_INIT 0x0000f0f0
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#define SARADC_REG10_INIT 0x70503010
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#define SARADC_REG11_INIT 0xf0d0b090
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#define SARADC_REG_NUM ((0x3c >> 2) + 2)
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#define SARADC_INTERRUPT_NUM IRQ_NUM_SEL2AO_AUX_ADC
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#endif
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