36 lines
559 B
C
36 lines
559 B
C
/*
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* Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef _CLK_H_
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#define _CLK_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum PLL_TYPE {
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PLL_SYS,
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PLL_GP0,
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PLL_GP1,
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PLL_FIX,
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PLL_HIFI,
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PLL_RTC,
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PLL_DDR
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};
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void disable_pll(int id);
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void set_time(uint32_t val);
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uint32_t get_time(void);
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void alt_timebase(int use_clk_src);
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void set_sys_div_clk(int sel, int div);
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void set_axi_div_clk(int sel, int div);
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void clk_util_set_dsp_clk(uint32_t id, uint32_t freq_sel);
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#ifdef __cplusplus
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}
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#endif
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#endif
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