172 lines
3.7 KiB
C
172 lines
3.7 KiB
C
/*
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* Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef __HW_CRYPTO_H__
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#define __HW_CRYPTO_H__
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//#include "secure_apb.h"
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#include "register.h"
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#include <stdint.h>
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#include <stddef.h>
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#include "interrupt.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef __unused
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#define __unused __maybe_unused
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#endif
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#define AML_CRYPTO_DEBUG (0)
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#define AML_CRYPTO_TEST (0)
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#define DMA_64_BIT (0)
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#define cryptCRYPTO_THREAD_IDX (4)
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#define configCryptoDmaUseIsr (0)
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#define DMA_TIME_OUT 10000
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#define UNSUPPORT_ADDR_START 0x10000000
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#define UNSUPPORT_ADDR_END 0x10008000
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#if AML_CRYPTO_TEST
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#define SZ 32
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#define MAGIC 0x87
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#define TEST_DDR_IN 0x1080000
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#define TEST_DDR_OUT 0x1090000
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#endif
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#if defined(BOARD_A1) || defined(BOARD_C1) || defined(BOARD_C2)
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#if cryptCRYPTO_THREAD_IDX >= 4
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#error "only 4 threads in A1"
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#endif
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#endif
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#define DMA_T0 DMA_CORE_DSC_0
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#define DMA_T1 DMA_CORE_DSC_1
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#define DMA_T2 DMA_CORE_DSC_2
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#define DMA_T3 DMA_CORE_DSC_3
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#define DMA_T4 DMA_CORE_DSC_4
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#define DMA_T5 DMA_CORE_DSC_5
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#define DMA_STS0 DMA_CORE_IRQ_STS_0
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#define DMA_STS1 DMA_CORE_IRQ_STS_1
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#define DMA_STS2 DMA_CORE_IRQ_STS_2
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#define DMA_STS3 DMA_CORE_IRQ_STS_3
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#define DMA_STS4 DMA_CORE_IRQ_STS_4
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#define DMA_STS5 DMA_CORE_IRQ_STS_5
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#define cryptIRQ_CRYPTO_DMA_THREAD_X \
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(IRQ_DMA_THREAD0 + cryptCRYPTO_THREAD_IDX)
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#define cryptDMA_THREAD_REG(thread) (DMA_T0 + (thread << 2))
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#define cryptDMA_STATUS_REG(thread) (DMA_STS0 + (thread << 2))
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#define cryptDMA_KEY_IV_LEN (0x30)
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enum aml_crypt_mode {
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AML_ENCRYPT = 0,
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AML_DECRYPT = 1
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};
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enum aml_opmode {
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MODE_ECB = 0,
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MODE_CBC = 1,
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MODE_CTR = 2
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};
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#define aml_crypt_mode_t enum aml_crypt_mode
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#define aml_opmode_t enum aml_opmode
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#define cryptAES_KEYSIZE_128 16
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#define cryptAES_KEYSIZE_192 24
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#define cryptAES_KEYSIZE_256 32
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#define cryptAES_BLOCK_SIZE 16
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/* definitions for dma */
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/* In block, which is 512 bytes */
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#define cryptMAX_BLOCK_TRANSFER (0x1fe00)
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#define cryptDMA_BLOCK_SIZE (0x200)
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#define cryptDMA_BLOCK_SIZE_SHIFT (9)
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#define cryptMAX_BLOCK_TRANSFER_LEN \
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(cryptMAX_BLOCK_TRANSFER * cryptDMA_BLOCK_SIZE)
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#define cryptKEY_IV_LEN (48)
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#define MAX_DESCRIPTORS (2)
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#define MAX_BYTES_TRANSFER (67239423) /* (2^17 - 1) * 512 + (2^17 - 1) */
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/* operation mode of DMA */
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#define cryptOP_MODE_SHA 0
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#define cryptOP_MODE_HMAC_I 1
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#define cryptOP_MODE_HMAC_O 2
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/* modes of DMA */
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#define cryptDMA_MODE_DMA 0x0
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#define cryptDMA_MODE_KEY 0x1
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#define cryptDMA_MODE_MEMSET 0x2
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/* 0x3 cryptDMA_MODE skipped */
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/* 0x4 cryptDMA_MODE skipped */
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#define cryptDMA_MODE_SHA1 0x5
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#define cryptDMA_MODE_SHA256 0x6
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#define cryptDMA_MODE_SHA224 0x7
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#define cryptDMA_MODE_AES128 0x8
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#define cryptDMA_MODE_AES192 0x9
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#define cryptDMA_MODE_AES256 0xa
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/* 0xb cryptDMA_MODE skipped */
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#define cryptDMA_MODE_DES 0xc
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/* 0xd cryptDMA_MODE skipped */
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#define cryptDMA_MODE_TDES_2K 0xe
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#define cryptDMA_MODE_TDES_3K 0xf
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#define cryptoDMA_STS_ERROR (0x02)
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#define cryptoDMA_STS_ERROR_REASON (0xfff0)
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#pragma pack(1)
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/* Main Descriptor */
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struct dma_dsc {
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union {
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uint32_t d32;
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struct {
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unsigned length:17;
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unsigned irq:1;
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unsigned eoc:1;
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unsigned loop:1;
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unsigned mode:4;
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unsigned begin:1;
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unsigned end:1;
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unsigned op_mode:2;
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unsigned enc_sha_only:1;
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unsigned block:1;
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unsigned link_error:1;
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unsigned owner:1;
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} b;
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} dsc_cfg;
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#if DMA_64_BIT
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uint64_t src_addr;
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uint64_t tgt_addr;
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#else
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uint32_t src_addr;
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uint32_t tgt_addr;
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#endif
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};
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#pragma pack(push, 1)
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struct vdma_info {
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uint32_t type;
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uint32_t size;
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void *src;
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void *dest;
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};
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#pragma pack(pop)
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void vVDMAInit(void);
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int xVDMATransfer(struct vdma_info *info);
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#if AML_CRYPTO_TEST
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void xDmaTest(uint32_t dir);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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