204 lines
5.5 KiB
C
204 lines
5.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_T3_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_T3_RESET_H
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/* RESET0 */
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/* 0-1 */
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#define RESET_U2PHY23 2
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#define RESET_U2PHY22 3
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#define RESET_USB 4
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#define RESET_U2DRD 5
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#define RESET_U3DRD 6
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#define RESET_U3DRD_PIPE0 7
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/* 8 */
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#define RESET_U2PHY21 9
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/* 10 */
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#define RESET_HDMI20_AES 11
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#define RESET_HDMIRX 12
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#define RESET_HDMIRX_APB 13
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/* 14 */
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#define RESET_VPU_HDMI_AXI 15
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/* 16 */
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#define RESET_BRG_VCBUS_DEC 17
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#define RESET_VCBUS 18
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#define RESET_VID_PLL_DIV 19
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#define RESET_VDI6_RST_N 20
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#define RESET_GE2D 21
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/* 22 */
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#define RESET_VID_LOCK 23
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#define RESET_VENC0 24
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#define RESET_VDAC 25
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#define RESET_VENC2 26
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#define RESET_VENC1 27
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#define RESET_RDMA 28
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/* 29 */
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#define RESET_VIU 30
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#define RESET_VENC 31
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/* RESET1 */
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#define RESET_AUDIOG 32
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#define RESET_MALI_CAPB3G 33
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#define RESET_MALIG 34
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#define RESET_DDRPLLG 35
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#define RESET_DMCG 36
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#define RESET_DOS_CAPB3G 37
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#define RESET_DOSG 38
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/* 39-40 */
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#define RESET_I_DEBUGA 41
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#define RESET_M31_UTMIG 42
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#define RESET_I_DSPA 43
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#define RESET_PCIE_AG 44
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#define RESET_PCIE_PHYG 45
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#define RESET_PCIE_APBG 46
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#define RESET_PCIEPHY_PIPEG 47
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#define RESET_ETHG 48
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/* 49-50 */
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#define RESET_COMBO_DPHY_CHAN0 51
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#define RESET_COMBO_DPHY_CHAN1 52
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/* 53-55 */
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#define RESET_DMC1G 56
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#define RESET_DEMODG 57
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/* 58-61 */
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#define RESET_DDR1PLLG 62
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/* 63 */
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/* RESET2 */
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/* 64 */
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#define RESET_RESET_N_IR_CTRL 65
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/* 66-67 */
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#define RESET_RESET_N_SPICC_2 68
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#define RESET_TCON 69
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/* 70-71 */
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#define RESET_SMART_CARD 72
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#define RESET_SPICC_0 73
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#define RESET_SPICC_1 74
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#define RESET_RSA 75
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/* 76 */
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#define RESET_FRC_APB 77
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#define RESET_FRC_RDMA 78
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#define RESET_FRC 79
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#define RESET_MSR_CLK 80
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#define RESET_SPIFC 81
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#define RESET_SAR_ADC 82
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#define RESET_BT 83
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/* 84-87 */
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#define RESET_ACODEC 88
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#define RESET_CEC 89
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#define RESET_AFIFO 90
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#define RESET_WATCHDOG 91
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/* 92 */
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#define RESET_TVFE 93
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#define RESET_ATV_DMD 94
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#define RESET_ADEC 95
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/* RESET3 */
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#define RESET_BRG_RSA_AP_PIPEL 96
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#define RESET_BRG_PCIETONOCDEV_PIPEL 97
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#define RESET_BRG_AMPIPE_NANA_RESETN 98
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#define RESET_BRG_CPUTONOCSYS_PIPEL 99
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/* 100-126*/
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#define RESET_A55_ACE 127
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/* RESET4 */
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/* 128-131 */
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#define RESET_PWM_AB 132
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#define RESET_PWM_CD 133
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#define RESET_PWM_EF 134
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#define RESET_PWM_GH 135
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#define RESET_PWM_IJ 136
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/* 137 */
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#define RESET_UART_A 138
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#define RESET_UART_B 139
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#define RESET_UART_C 140
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#define RESET_UART_D 141
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#define RESET_NNA 142
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#define RESET_CIPLUS 143
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#define RESET_I2C_S_A 144
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#define RESET_I2C_M_A 145
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#define RESET_I2C_M_B 146
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#define RESET_I2C_M_C 147
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#define RESET_I2C_M_D 148
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#define RESET_I2C_M_E 149
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/* 150-152 */
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#define RESET_SD_EMMC_B 153
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#define RESET_SD_EMMC_C 154
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/* 155 */
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#define RESET_TS_CPU 156
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#define RESET_TS_NNA 157
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#define RESET_TS_VPU 158
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/* 159 */
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/* RESET5 */
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#define RESET_BRG_NOCDDR_DDR1 160
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#define RESET_BRG_NOCDDR_DDR0 161
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#define RESET_BRG_NOCDDR_MAIN 162
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#define RESET_BRG_NOCDDR_ALL 163
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#define RESET_BRG_NOCDDR_GPU 164
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#define RESET_BRG_NOCDDR_CPU 165
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#define RESET_BRG_NOCDDR_NNA 166
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/* 167 */
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#define RESET_BRG_NOCDEV_SYS 168
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#define RESET_BRG_NOCDEV_MAIN 169
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#define RESET_BRG_NOCDEV_HDMI 170
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#define RESET_BRG_NOCDEV_ALL 171
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/* 172 */
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#define RESET_BRG_NOCDOS_VDEC 173
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#define RESET_BRG_NOCDOS_HECVF 174
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#define RESET_BRG_NOCDOS_HEVCB 175
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#define RESET_BRG_NOCDOS_HCODEC 176
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#define RESET_BRG_NOCDOS_GE2D 177
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/* 178 */
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#define RESET_BRG_NOCDOS_SYS 179
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#define RESET_BRG_NOCDOS_MAIN 180
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#define RESET_BRG_NOCDOS_ALL 181
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#define RESET_BRG_NOCVPU_MAIN 182
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#define RESET_BRG_NOCVPU_ALL 183
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#define RESET_BRG_NOCVPU_SYS 184
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#define RESET_BRG_NOCSYS_CPU 185
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/* 186 */
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#define RESET_BRG_NOCSYS_DSPA 187
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#define RESET_BRG_NOCSYS_VAPB 188
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#define RESET_BRG_NOCSYS_SYS 189
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#define RESET_BRG_NOCSYS_MAIN 190
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#define RESET_BRG_NOCSYS_ALL 191
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/* RESET6 */
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#define RESET_BRG_VDEC_PIPEL 192
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#define RESET_BRG_HEVCF_DMC_PIPEL 193
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#define RESET_BRG_VPU_TOP_APB_PIPEL 194
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#define RESET_BRG_HDMIRXTONOCDEV_PIPEL 195
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#define RESET_BRG_MALITONOCDDR_PIPEL 196
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#define RESET_BRG_NOCVPUTONOCDDR_PIPEL 197
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#define RESET_BRG_NOCSYSTONOCDDR_PIPEL 198
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#define RESET_BRG_NOCDOSTONOCDDR_PIPEL 199
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#define RESET_BRG_NOCDEVTONOCDDR_PIPEL 200
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#define RESET_BRG_CPUTONOCDDR_PIPEL 201
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/* 202 */
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#define RESET_BRG_NOCDOS_APB_PIPEL 203
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/* 204 */
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#define RESET_BRG_DSPTONOCSYS_PIPEL 205
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#define RESET_BRG_USB3TONOCDEV_PIPEL 206
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#define RESET_BRG_USB2TONOCDEV_PIPEL 207
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#define RESET_BRG_ETH_HDMIRX_APB_PIPEL 208
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#define RESET_BRG_DOS_APB_PIPEL 209
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#define RESET_BRG_GE2D_APB_PIPEL 210
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#define RESET_BRG_ACODEC_APB_PIPEL 211
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#define RESET_BRG_USB_PCIE_CTRL_APB_PIPEL 212
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#define RESET_BRG_USB_PCIE_PHY_APB_PIPEL 213
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#define RESET_BRG_ETH_AHB_PIPEL 214
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#define RESET_BRG_USB0_AHB_PIPEL 215
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#define RESET_BRG_USB1_AHB_PIPEL 216
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#define RESET_BRG_USB2_AHB_PIPEL 217
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#define RESET_BRG_USB2DEVTONOCDEV_AHB_PIPEL 218
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#define RESET_BRG_AMPIPE_ETH_RESETN 219
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#define RESET_BRG_FRC_TOP_APB_PIPEL 220
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#define RESET_BRG_AM2AXI0_RESETN 221
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#define RESET_BRG_AM2AXI1_RESETN 222
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#define RESET_BRG_AM2AXI2_RESETN 223
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#endif
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