172 lines
4.3 KiB
C
172 lines
4.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_S6_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_S6_RESET_H
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/* RESET0 */
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/* 0-1 */
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#define RESET_U3DRD_USB3PHY_APB 2
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#define RESET_U3DRD_USB3PHY 3
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#define RESET_U3DRD_USB2PHY 4
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#define RESET_U3DRD 5
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#define RESET_U3DRD_COMB 6
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#define RESET_U2DRD 7
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#define RESET_U2DRD_COMB 8
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#define RESET_U2DRD_USB2PHY 9
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#define RESET_USB_CC 10
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#define RESET_BC 11
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#define RESET_VC9000E_APB 12
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#define RESET_VC9000E 13
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#define RESET_VC9000E_CORE 14
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#define RESET_HDMI20_AES 15
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#define RESET_HDMITX_CAPB3 16
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#define RESET_BRQ_VCBUS_DEC 17
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#define RESET_VCBUS 18
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#define RESET_VID_PLL_DIV 19
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#define RESET_VDI6 20
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/* 21 */
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#define RESET_HDMITXPHY 22
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#define RESET_VID_LOCK 23
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#define RESET_VENCL 24
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#define RESET_VDAC 25
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#define RESET_VENCP 26
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#define RESET_VENCI 27
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#define RESET_RDMA 28
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#define RESET_HDMITX 29
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#define RESET_VIU 30
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#define RESET_VENC 31
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/* RESET1 */
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#define RESET_AUDIO 32
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#define RESET_MAIL_CAPB3 33
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#define RESET_MAIL 34
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#define RESET_DDR_APB 35
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#define RESET_DDR 36
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#define RESET_DOS_CAPB3 37
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#define RESET_DOS 38
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#define RESET_MALI_SYS 39
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#define RESET_I_DSPA 40
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#define RESET_I_DEBUGA 41
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#define RESET_U3P2_PHY_APB 42
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#define RESET_PCIE_PIPE 43
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#define RESET_PCIE_A 44
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#define RESET_PCIE_PHY 45
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#define RESET_PCIE_APB 46
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#define RESET_AMFC_APB 47
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#define RESET_ETHERNET 48
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/* 49-50 */
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#define RESET_BRG_ETH_APB_SYNC 51
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#define RESET_VICP 52
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#define RESET_DEWARP 53
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#define RESET_GE2D 54
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#define RESET_VGE 55
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#define RESET_PCIE0 56
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#define RESET_PCIE1 57
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#define RESET_PCIE2 58
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#define RESET_PCIE3 59
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#define RESET_PCIE4 60
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#define RESET_PCIE5 61
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#define RESET_PCIE6 62
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#define RESET_PCIE7 63
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/* RESET2 */
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#define RESET_AM2AXI 64
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#define RESET_IR_CTRL 65
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#define RESET_MIPI_DSI_PHY 66
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#define RESET_TS_PLL 67
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#define RESET_MIPI_CSI2_PHY0 68
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#define RESET_ETH_AXI 69
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/* 70-71 */
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#define RESET_SMART_CARD 72
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#define RESET_SPICC_0 73
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#define RESET_BRG_VGE_PIPEL1 74
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#define RESET_BRG_VC9000E_PIPEL1 75
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#define RESET_BRG_AMFC_PIPEL1 76
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/* 77 */
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#define RESET_NNA_APB 78
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#define RESET_NNA 79
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#define RESET_MSR_CLK 80
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/* 81 */
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#define RESET_SAR_DIG 82
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#define RESET_SAR_ANA 83
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/* 84-85 */
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#define RESET_AMFC 86
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/* 87-88 */
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#define RESET_CEC 89
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/* 90 */
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#define RESET_WATCHDOG 91
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/* 92 */
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#define RESET_MIP_DSI_HOST 93
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/* 94-95 */
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/* RESET3 */
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/* 96 ~ 127 */
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/* RESET4 */
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#define RESET_PWM_A 128
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#define RESET_PWM_B 129
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#define RESET_PWM_C 130
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#define RESET_PWM_D 131
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#define RESET_PWM_E 132
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#define RESET_PWM_F 133
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#define RESET_PWM_G 134
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#define RESET_PWM_H 135
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#define RESET_PWM_I 136
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#define RESET_PWM_J 137
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#define RESET_UART_A 138
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#define RESET_UART_B 139
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#define RESET_UART_C 140
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#define RESET_UART_D 141
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#define RESET_UART_E 142
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/* 143 */
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#define RESET_I2C_S_A 144
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#define RESET_I2C_M_A 145
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#define RESET_I2C_M_B 146
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#define RESET_I2C_M_C 147
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#define RESET_I2C_M_D 148
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#define RESET_I2C_M_E 149
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/* 150-151 */
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#define RESET_SDEMMC_A 152
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#define RESET_SDEMMC_B 153
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#define RESET_SDEMMC_C 154
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/* 155-159 */
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/* RESET5 */
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#define RESET_BRG_VDEC_PIPEL 160
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#define RESET_BRG_SDIOA_PIPEL 161
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#define RESET_BRG_SDIOB_PIPEL 162
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#define RESET_BRG_EMMC_PIPEL 163
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#define RESET_BRG_GE2D_DMC_PIPEL 164
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#define RESET_BRG_DMC_VPU_PIPEL1 165
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#define RESET_BRG_A53_DMC_PIPEL1 166
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#define RESET_BRG_MAIL_DMC_PIPEL 167
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/* 168 */
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#define RESET_BRG_MAIL_DMC_PIPEL1 169
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#define RESET_BRG_U2DRD_PIPEL 170
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#define RESET_BRG_U2H_PIPEL 171
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#define RESET_BRG_HEVCF_PIPEL1 172
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#define RESET_BRG_AMBUS_ETH_PIPEL1 173
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#define RESET_BRG_SRAM_NIC_NNA 174
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#define RESET_BRG_SRAM_NIC_MAIN 175
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#define RESET_BRG_SRAM_NIC_DEV 176
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#define RESET_BRG_SRAM_NIC_CPU 177
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#define RESET_BRG_SRAM_NIC_ALL 178
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#define RESET_BRG_CPU_NIC_RAMA 179
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#define RESET_BRG_CPU_NIC_VAPB 180
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#define RESET_BRG_CPU_NIC_DSU 181
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#define RESET_BRG_CPU_NIC_CLK81 182
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#define RESET_BRG_CPU_NIC_ALL 183
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#define RESET_BRG_NIC_CAPU 184
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#define RESET_BRG_AO_NIC_EMMC 185
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#define RESET_BRG_AO_NIC_DSPA 186
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#define RESET_BRG_AO_NIC_SDIOB 187
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#define RESET_BRG_AO_NIC_SDIOA 188
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#define RESET_BRG_AO_NIC_CLK81 189
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#define RESET_BRG_AO_NIC_MAIN 190
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#define RESET_BRG_AO_NIC_ALL 191
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#endif
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