222 lines
5.6 KiB
C
222 lines
5.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_S5_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_S5_RESET_H
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/* RESET0 */
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/* 0 */
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#define RESET_U3X1_M31_UTMI 1
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#define RESET_U3X0_M31_UTMI 2
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#define RESET_U2DRDX0 3
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/* 4 */
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#define RESET_U3DRDX1 5
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#define RESET_U3DRDX0 6
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/* 7 */
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#define RESET_U2PHY20 8
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#define RESET_U3X1_PCIE_PHY 9
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#define RESET_U3X0_PCIE_PHY 10
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#define RESET_APB_DECODE_DMC 11
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/* 12-15 */
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#define RESET_BRG_SYS_APB_DEC 16
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#define RESET_BRG_VCBUS_DEC 17
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#define RESET_HDMITX_CAPB3 18
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#define RESET_HDMITX 19
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/* 20 */
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#define RESET_GE2D 21
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/* 22 */
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#define RESET_HTXDPHY 23
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#define RESET_HDMI20_AES 24
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/* 25-28 */
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#define RESET_DSC_ENC_CAPB3 29
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#define RESET_DSC_ENC 30
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/* 31 */
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/* RESET1 */
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#define RESET_AUDIO 32
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#define RESET_DOS 33
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#define RESET_DOS_CAPB3 34
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#define RESET_DDR_APB 35
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#define RESET_DDR 36
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/* 37 */
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#define RESET_U3X1_PCIE_APB 38
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#define RESET_U3X0_PCIE_APB 39
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#define RESET_I_DEBUGB 40
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#define RESET_I_DEBUGA 41
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/* 42-43 */
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#define RESET_PCIE_GEN2_L1 44
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#define RESET_PCIE_B_APB 45
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#define RESET_PCIE_A_APB 46
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#define RESET_ADLA 47
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#define RESET_ETH 48
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/* 49 */
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#define RESET_PCIE_GEN2_L0 50
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/* 51 */
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#define RESET_U3COMBX1 52
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#define RESET_U3COMBX0 53
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#define RESET_U2COMBX0 54
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#define RESET_NNA_NIC_4T 55
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/* 56-58 */
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#define RESET_NNA_NIC_1T 59
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#define RESET_NNA_NIC_MAIN 60
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#define RESET_NNA_NIC_GPV 61
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#define RESET_NNA_NIC_ALL 62
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#define RESET_ACODEC 63
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/* RESET2 */
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#define RESET_IR_CTRL 64
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#define RESET_TS_A55 65
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/* 66-67 */
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#define RESET_SPICC_2 68
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/* 69-71 */
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#define RESET_SMART_CARD 72
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#define RESET_SPICC_0 73
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#define RESET_SPICC_1 74
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/* 75-79 */
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#define RESET_MSR_CLK 80
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#define RESET_SPIFC 81
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#define RESET_SAR_ADC 82
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/* 83-88 */
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#define RESET_CEC 89
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#define RESET_AFIFO 90
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#define RESET_WATCHDOG 91
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#define RESET_VID_PLL0_DIV 92
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/* 93 */
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#define RESET_TMDS20_DIV 94
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/* 95 */
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/* RESET3 */
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/* 96-99 */
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#define RESET_PCIE_B_7 100
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#define RESET_PCIE_B_6 101
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#define RESET_PCIE_B_5 102
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#define RESET_PCIE_B_4 103
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#define RESET_PCIE_B_3 104
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#define RESET_PCIE_B_2 105
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#define RESET_PCIE_B_1 106
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#define RESET_PCIE_B_0 107
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#define RESET_PCIE_A_7 108
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#define RESET_PCIE_A_6 109
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#define RESET_PCIE_A_5 110
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#define RESET_PCIE_A_4 111
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#define RESET_PCIE_A_3 112
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#define RESET_PCIE_A_2 113
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#define RESET_PCIE_A_1 114
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#define RESET_PCIE_A_0 115
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#define RESET_VDI6 116
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#define RESET_VID_LOCK 117
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#define RESET_VENC2 118
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#define RESET_VENC1 119
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#define RESET_VENC0 120
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#define RESET_VDAC 121
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#define RESET_RDMA 122
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#define RESET_VIU 123
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#define RESET_VENC 124
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/* 125-126 */
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#define RESET_A55_ACE 127
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/* RESET4 */
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#define RESET_PWM_AB 128
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#define RESET_PWM_CD 129
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#define RESET_PWM_EF 130
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#define RESET_PWM_GH 131
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#define RESET_PWM_IJ 132
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#define RESET_VID_CMPR 133
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#define RESET_VC9000E_ARESET 134
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#define RESET_VC9000E_CORE 135
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/* 136 */
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#define RESET_VC9000E_APB 137
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#define RESET_UART_A 138
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#define RESET_UART_B 139
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#define RESET_UART_C 140
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#define RESET_UART_D 141
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#define RESET_UART_E 142
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#define RESET_UART_F 143
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#define RESET_I2C_S_A 144
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#define RESET_I2C_M_A 145
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#define RESET_I2C_M_B 146
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#define RESET_I2C_M_C 147
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#define RESET_I2C_M_D 148
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#define RESET_I2C_M_E 149
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#define RESET_I2C_M_F 150
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/* 151 */
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#define RESET_UART_G 152
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#define RESET_SD_EMMC_A 153
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#define RESET_SD_EMMC_B 154
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#define RESET_SD_EMMC_C 155
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#define RESET_TS_GPU 156
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#define RESET_TS_NNA 157
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#define RESET_TS_VPU 158
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#define RESET_TS_DOS 159
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/* RESET5 */
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/* 160-177 */
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#define RESET_BRG_NICSYS_NPU 178
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#define RESET_BRG_NICSYS_EMMCC 179
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#define RESET_BRG_NICSYS_EMMCB 180
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#define RESET_BRG_NICSYS_EMMCA 181
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/* 182 */
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#define RESET_BRG_NICSYS_PCIE 183
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#define RESET_BRG_NICSYS_SYSCPU 184
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#define RESET_BRG_NICSYS_SYS 185
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/* 186-188 */
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#define RESET_BRG_NICSYS_VAPB 189
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#define RESET_BRG_NICSYS_MAIN 190
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#define RESET_BRG_NICSYS_ALL 191
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/* RESET6 */
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#define RESET_BRG_AHB_PIPE_NICDOS 192
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#define RESET_BRG_AHB_PIPE_NICNNA 193
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#define RESET_BRG_AHB_PIPE_NICVPU 194
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#define RESET_BRG_AHB_PIPE_NICVGE 195
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/* 196 */
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#define RESET_BRG_AHB_PIPE_NICSYS 197
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#define RESET_BRG_VDEC_DMC_PIPEL 198
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#define RESET_BRG_HEVCF_DMC_PIPEL 199
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/* 200 */
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#define RESET_BRG_AXI_PIPE_NNATODDR 201
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/* 202 */
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#define RESET_BRG_AXI_PIPE_NNATOSYS 203
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#define RESET_BRG_AXI_PIPE_NICVPU 204
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#define RESET_BRG_AXI_PIPE_NICDOS 205
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#define RESET_BRG_AXI_PIPE_NICVGE 206
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#define RESET_BRG_AXI_PIPE_EMMCC 207
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#define RESET_BRG_APB_PIPE_NNA 208
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#define RESET_BRG_APB_PIPE_FDLETOP 209
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#define RESET_BRG_APB_PIPE_NOCDMC 210
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#define RESET_BRG_APB_PIPE_DDR0 211
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#define RESET_BRG_APB_PIPE_DDR1 212
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#define RESET_BRG_APB_PIPE_GE2D 213
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#define RESET_BRG_APB_PIPE_VPU 214
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/* 215-217 */
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#define RESET_BRG_AMPIPE_NAND 218
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#define RESET_BRG_AMPIPE_ETH 219
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/* 220 */
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#define RESET_BRG_AM2AXI0 221
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/* 222-223 */
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/* RESET7 */
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/* 224-234 */
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#define RESET_BRG_NICVGE_SYS 235
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#define RESET_BRG_NICVGE_VC9000E 236
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#define RESET_BRG_NICVGE_VID_CMPR 237
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#define RESET_BRG_NICVGE_GE2D 238
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/* 239-241 */
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#define RESET_BRG_NICVGE_MAIN 242
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#define RESET_BRG_NICVGE_ALL 243
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/* 244 */
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#define RESET_BRG_NICDOS_SYS 245
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#define RESET_BRG_NICDOS_VDEC 246
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#define RESET_BRG_NICDOS_HEVC 247
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#define RESET_BRG_NICDOS_HCODEC 248
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#define RESET_BRG_NICDOS_MAIN 249
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#define RESET_BRG_NICDOS_ALL 250
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/* 251-252 */
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#define RESET_BRG_NICVPU_SYS 253
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#define RESET_BRG_NICVPU_MAIN 254
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#define RESET_BRG_NICVPU_ALL 255
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#endif
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