94 lines
2.4 KiB
C
94 lines
2.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __A9_MBOX_H__
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#define __A9_MBOX_H__
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#include "amlogic,mbox.h"
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/* MAILBOX DRIVER ID */
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/* AOCPU to ARMREE driver ID */
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#define A9_AO2REE0 0
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#define A9_AO2REE1 1
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#define A9_AO2REE2 2
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#define A9_AO2REE3 3
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#define A9_AO2REE4 4
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#define A9_AO2REE5 5
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#define A9_AO2REE6 6
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#define A9_AO2REE7 7
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#define A9_AO2REE8 8
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#define A9_AO2REE9 9
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#define A9_AO2REE10 10
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/* ARMREE to AOCPU driver ID */
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#define A9_REE2AO0 64
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#define A9_REE2AO1 65
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#define A9_REE2AO2 66
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#define A9_REE2AO3 67
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#define A9_REE2AO4 68
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#define A9_REE2AO5 69
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#define A9_REE2AO6 70
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#define A9_REE2AO7 71
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#define A9_REE2AO8 72
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#define A9_REE2AO9 73
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#define A9_REE2AO10 74
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/* DSPA to ARMREE driver ID */
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#define A9_DSPA2REE0 129
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#define A9_DSPA2REE1 130
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#define A9_DSPA2REE2 131
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#define A9_DSPA2REE3 132
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#define A9_DSPA2REE4 133
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/* ARMREE to DSPA driver ID */
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#define A9_REE2DSPA0 161
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#define A9_REE2DSPA1 162
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#define A9_REE2DSPA2 163
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#define A9_REE2DSPA3 164
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#define A9_REE2DSPA4 165
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/* MBOX CLIENT ID */
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/* AOCPU to ARMREE client ID */
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#define A9_AO2REE_DEV A9_AO2REE0
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#define A9_AO2REE_VRTC A9_AO2REE1
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#define A9_AO2REE_RTC A9_AO2REE2
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#define A9_AO2REE_KEYPAD A9_AO2REE3
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#define A9_AO2REE_AOCEC A9_AO2REE4
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#define A9_AO2REE_LED A9_AO2REE5
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#define A9_AO2REE_ETH A9_AO2REE6
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#define A9_AO2REE_SPINLOCK A9_AO2REE7
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/* ARMREE to AOCPU client ID */
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#define A9_REE2AO_DRV A9_REE2AO0
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#define A9_REE2AO_DEV A9_REE2AO1
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#define A9_REE2AO_VRTC A9_REE2AO2
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#define A9_REE2AO_RTC A9_REE2AO3
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#define A9_REE2AO_KEYPAD A9_REE2AO4
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#define A9_REE2AO_AOCEC A9_REE2AO5
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#define A9_REE2AO_LED A9_REE2AO6
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#define A9_REE2AO_ETH A9_REE2AO7
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#define A9_REE2AO_SPINLOCK A9_REE2AO8
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#define A9_REE2AO_IR A9_REE2AO9
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/* ARMREE to DSPA client ID */
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#define A9_REE2DSPA_DEV A9_REE2DSPA0
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#define A9_REE2DSPA_HOST A9_REE2DSPA1
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/* DSPA to ARMREE client ID */
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#define A9_DSPA2REE_DEV A9_DSPA2REE0
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#define A9_DSPA2REE_HOST A9_DSPA2REE1
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/* MBOX CHANNEL ID */
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#define A9_MBOX_DSPA2REE 0
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#define A9_MBOX_REE2DSPA 1
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#define A9_MBOX_AO2REE 2
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#define A9_MBOX_REE2AO 3
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#define A9_MBOX_NUMS 4
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/* AOCPU STATUS MBOX CHANNEL ID */
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#define A9_AOCPU_STS_CHAN 4
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#endif /* __A9_MBOX_H__ */
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