303 lines
12 KiB
C
303 lines
12 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __S7_CLKC_H
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#define __S7_CLKC_H
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/*
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* CLKID index values
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*/
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#define CLKID_PLL_BASE 0
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#define CLKID_FIXED_PLL_DCO (CLKID_PLL_BASE + 0)
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#define CLKID_FIXED_PLL (CLKID_PLL_BASE + 1)
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#define CLKID_FCLK_DIV2_DIV (CLKID_PLL_BASE + 2)
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#define CLKID_FCLK_DIV2 (CLKID_PLL_BASE + 3)
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#define CLKID_FCLK_DIV3_DIV (CLKID_PLL_BASE + 4)
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#define CLKID_FCLK_DIV3 (CLKID_PLL_BASE + 5)
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#define CLKID_FCLK_DIV4_DIV (CLKID_PLL_BASE + 6)
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#define CLKID_FCLK_DIV4 (CLKID_PLL_BASE + 7)
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#define CLKID_FCLK_DIV5_DIV (CLKID_PLL_BASE + 8)
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#define CLKID_FCLK_DIV5 (CLKID_PLL_BASE + 9)
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#define CLKID_FCLK_DIV7_DIV (CLKID_PLL_BASE + 10)
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#define CLKID_FCLK_DIV7 (CLKID_PLL_BASE + 11)
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#define CLKID_FCLK_DIV2P5_DIV (CLKID_PLL_BASE + 12)
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#define CLKID_FCLK_DIV2P5 (CLKID_PLL_BASE + 13)
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#define CLKID_FCLK_CLK50M_DIV (CLKID_PLL_BASE + 14)
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#define CLKID_FCLK_CLK50M (CLKID_PLL_BASE + 15)
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#define CLKID_GP0_PLL_DCO (CLKID_PLL_BASE + 16)
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#define CLKID_GP0_PLL (CLKID_PLL_BASE + 17)
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#define CLKID_PLL1_BASE (CLKID_PLL_BASE + 18)
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#define CLKID_HIFI_PLL_DCO (CLKID_PLL1_BASE + 0)
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#define CLKID_HIFI_PLL (CLKID_PLL1_BASE + 1)
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#define CLKID_HIFI1_PLL_DCO (CLKID_PLL1_BASE + 2)
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#define CLKID_HIFI1_PLL (CLKID_PLL1_BASE + 3)
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#define CLKID_BASE (CLKID_PLL1_BASE + 4)
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#define CLKID_RTC_DUAL_CLKIN (CLKID_BASE + 0)
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#define CLKID_RTC_DUAL_DIV (CLKID_BASE + 1)
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#define CLKID_RTC_DUAL_SEL (CLKID_BASE + 2)
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#define CLKID_RTC_DUAL_CLKOUT (CLKID_BASE + 3)
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#define CLKID_RTC_CLK (CLKID_BASE + 4)
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#define CLKID_SYS_CLK_0_SEL (CLKID_BASE + 5)
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#define CLKID_SYS_CLK_0_DIV (CLKID_BASE + 6)
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#define CLKID_SYS_CLK_0 (CLKID_BASE + 7)
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#define CLKID_SYS_CLK_1_SEL (CLKID_BASE + 8)
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#define CLKID_SYS_CLK_1_DIV (CLKID_BASE + 9)
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#define CLKID_SYS_CLK_1 (CLKID_BASE + 10)
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#define CLKID_SYS_CLK (CLKID_BASE + 11)
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#define CLKID_AXI_CLK_0_SEL (CLKID_BASE + 12)
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#define CLKID_AXI_CLK_0_DIV (CLKID_BASE + 13)
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#define CLKID_AXI_CLK_0 (CLKID_BASE + 14)
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#define CLKID_AXI_CLK_1_SEL (CLKID_BASE + 15)
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#define CLKID_AXI_CLK_1_DIV (CLKID_BASE + 16)
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#define CLKID_AXI_CLK_1 (CLKID_BASE + 17)
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#define CLKID_AXI_CLK (CLKID_BASE + 18)
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#define CLKID_CECB_DUAL_CLKIN (CLKID_BASE + 19)
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#define CLKID_CECB_DUAL_DIV (CLKID_BASE + 20)
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#define CLKID_CECB_DUAL_SEL (CLKID_BASE + 21)
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#define CLKID_CECB_DUAL_CLKOUT (CLKID_BASE + 22)
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#define CLKID_CECB_CLK (CLKID_BASE + 23)
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#define CLKID_SC_SEL (CLKID_BASE + 24)
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#define CLKID_SC_DIV (CLKID_BASE + 25)
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#define CLKID_SC (CLKID_BASE + 26)
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#define CLKID_12_24M_IN (CLKID_BASE + 27)
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#define CLKID_12_24M (CLKID_BASE + 28)
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#define CLKID_VCLK_SEL (CLKID_BASE + 29)
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#define CLKID_VCLK2_SEL (CLKID_BASE + 30)
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#define CLKID_VCLK_INPUT (CLKID_BASE + 31)
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#define CLKID_VCLK2_INPUT (CLKID_BASE + 32)
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#define CLKID_VCLK_DIV (CLKID_BASE + 33)
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#define CLKID_VCLK2_DIV (CLKID_BASE + 34)
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#define CLKID_VCLK (CLKID_BASE + 35)
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#define CLKID_VCLK2 (CLKID_BASE + 36)
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#define CLKID_VCLK_DIV1 (CLKID_BASE + 37)
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#define CLKID_VCLK_DIV2_EN (CLKID_BASE + 38)
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#define CLKID_VCLK_DIV4_EN (CLKID_BASE + 39)
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#define CLKID_VCLK_DIV6_EN (CLKID_BASE + 40)
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#define CLKID_VCLK_DIV12_EN (CLKID_BASE + 41)
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#define CLKID_VCLK2_DIV1 (CLKID_BASE + 42)
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#define CLKID_VCLK2_DIV2_EN (CLKID_BASE + 43)
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#define CLKID_VCLK2_DIV4_EN (CLKID_BASE + 44)
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#define CLKID_VCLK2_DIV6_EN (CLKID_BASE + 45)
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#define CLKID_VCLK2_DIV12_EN (CLKID_BASE + 46)
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#define CLKID_VCLK_DIV2 (CLKID_BASE + 47)
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#define CLKID_VCLK_DIV4 (CLKID_BASE + 48)
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#define CLKID_VCLK_DIV6 (CLKID_BASE + 49)
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#define CLKID_VCLK_DIV12 (CLKID_BASE + 50)
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#define CLKID_VCLK2_DIV2 (CLKID_BASE + 51)
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#define CLKID_VCLK2_DIV4 (CLKID_BASE + 52)
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#define CLKID_VCLK2_DIV6 (CLKID_BASE + 53)
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#define CLKID_VCLK2_DIV12 (CLKID_BASE + 54)
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#define CLKID_ENCI_SEL (CLKID_BASE + 55)
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#define CLKID_ENCL_SEL (CLKID_BASE + 56)
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#define CLKID_ENCP_SEL (CLKID_BASE + 57)
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#define CLKID_VDAC_SEL (CLKID_BASE + 58)
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#define CLKID_HDMI_TX_PIXEL_SEL (CLKID_BASE + 59)
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#define CLKID_HDMI_TX_FE_SEL (CLKID_BASE + 60)
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#define CLKID_ENCI (CLKID_BASE + 61)
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#define CLKID_ENCL (CLKID_BASE + 62)
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#define CLKID_ENCP (CLKID_BASE + 63)
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#define CLKID_VDAC (CLKID_BASE + 64)
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#define CLKID_HDMI_TX_PIXEL (CLKID_BASE + 65)
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#define CLKID_HDMI_TX_FE (CLKID_BASE + 66)
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#define CLKID_LCD_AN_CLK_PH23_SEL (CLKID_BASE + 67)
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#define CLKID_LCD_AN_CLK_PH23 (CLKID_BASE + 68)
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#define CLKID_LCD_AN_CLK_PH2 (CLKID_BASE + 69)
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#define CLKID_LCD_AN_CLK_PH3 (CLKID_BASE + 70)
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#define CLKID_HDMI_TX_SYS_SEL (CLKID_BASE + 71)
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#define CLKID_HDMI_TX_SYS_DIV (CLKID_BASE + 72)
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#define CLKID_HDMI_TX_SYS (CLKID_BASE + 73)
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#define CLKID_HDMI_TX_PRIF_SEL (CLKID_BASE + 74)
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#define CLKID_HDMI_TX_PRIF_DIV (CLKID_BASE + 75)
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#define CLKID_HDMI_TX_PRIF (CLKID_BASE + 76)
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#define CLKID_HDMI_TX_200M_SEL (CLKID_BASE + 77)
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#define CLKID_HDMI_TX_200M_DIV (CLKID_BASE + 78)
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#define CLKID_HDMI_TX_200M (CLKID_BASE + 79)
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#define CLKID_HDMI_TX_AUD_SEL (CLKID_BASE + 80)
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#define CLKID_HDMI_TX_AUD_DIV (CLKID_BASE + 81)
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#define CLKID_HDMI_TX_AUD (CLKID_BASE + 82)
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#define CLKID_VID_LOCK_SEL (CLKID_BASE + 83)
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#define CLKID_VID_LOCK_DIV (CLKID_BASE + 84)
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#define CLKID_VID_LOCK (CLKID_BASE + 85)
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#define CLKID_ETH_RMII_DIV (CLKID_BASE + 86)
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#define CLKID_ETH_RMII (CLKID_BASE + 87)
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#define CLKID_ETH_125M_DIV8 (CLKID_BASE + 88)
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#define CLKID_ETH_125M (CLKID_BASE + 89)
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#define CLKID_TS_DIV (CLKID_BASE + 90)
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#define CLKID_TS (CLKID_BASE + 91)
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#define CLKID_MALI_0_SEL (CLKID_BASE + 92)
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#define CLKID_MALI_0_DIV (CLKID_BASE + 93)
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#define CLKID_MALI_0 (CLKID_BASE + 94)
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#define CLKID_MALI_1_SEL (CLKID_BASE + 95)
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#define CLKID_MALI_1_DIV (CLKID_BASE + 96)
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#define CLKID_MALI_1 (CLKID_BASE + 97)
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#define CLKID_MALI (CLKID_BASE + 98)
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#define CLKID_VDEC_0_SEL (CLKID_BASE + 99)
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#define CLKID_VDEC_0_DIV (CLKID_BASE + 100)
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#define CLKID_VDEC_0 (CLKID_BASE + 101)
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#define CLKID_VDEC_1_SEL (CLKID_BASE + 102)
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#define CLKID_VDEC_1_DIV (CLKID_BASE + 103)
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#define CLKID_VDEC_1 (CLKID_BASE + 104)
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#define CLKID_VDEC (CLKID_BASE + 105)
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#define CLKID_HEVCF_0_SEL (CLKID_BASE + 106)
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#define CLKID_HEVCF_0_DIV (CLKID_BASE + 107)
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#define CLKID_HEVCF_0 (CLKID_BASE + 108)
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#define CLKID_HEVCF_1_SEL (CLKID_BASE + 109)
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#define CLKID_HEVCF_1_DIV (CLKID_BASE + 110)
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#define CLKID_HEVCF_1 (CLKID_BASE + 111)
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#define CLKID_HEVCF (CLKID_BASE + 112)
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#define CLKID_VPU_0_SEL (CLKID_BASE + 113)
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#define CLKID_VPU_0_DIV (CLKID_BASE + 114)
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#define CLKID_VPU_0 (CLKID_BASE + 115)
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#define CLKID_VPU_1_SEL (CLKID_BASE + 116)
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#define CLKID_VPU_1_DIV (CLKID_BASE + 117)
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#define CLKID_VPU_1 (CLKID_BASE + 118)
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#define CLKID_VPU (CLKID_BASE + 119)
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#define CLKID_VPU_CLKB_TMP_SEL (CLKID_BASE + 120)
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#define CLKID_VPU_CLKB_TMP_DIV (CLKID_BASE + 121)
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#define CLKID_VPU_CLKB_TMP (CLKID_BASE + 122)
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#define CLKID_VPU_CLKB_DIV (CLKID_BASE + 123)
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#define CLKID_VPU_CLKB (CLKID_BASE + 124)
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#define CLKID_VPU_CLKC_0_SEL (CLKID_BASE + 125)
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#define CLKID_VPU_CLKC_0_DIV (CLKID_BASE + 126)
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#define CLKID_VPU_CLKC_0 (CLKID_BASE + 127)
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#define CLKID_VPU_CLKC_1_SEL (CLKID_BASE + 128)
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#define CLKID_VPU_CLKC_1_DIV (CLKID_BASE + 129)
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#define CLKID_VPU_CLKC_1 (CLKID_BASE + 130)
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#define CLKID_VPU_CLKC (CLKID_BASE + 131)
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#define CLKID_VAPB_0_SEL (CLKID_BASE + 132)
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#define CLKID_VAPB_0_DIV (CLKID_BASE + 133)
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#define CLKID_VAPB_0 (CLKID_BASE + 134)
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#define CLKID_VAPB_1_SEL (CLKID_BASE + 135)
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#define CLKID_VAPB_1_DIV (CLKID_BASE + 136)
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#define CLKID_VAPB_1 (CLKID_BASE + 137)
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#define CLKID_VAPB (CLKID_BASE + 138)
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#define CLKID_GE2D (CLKID_BASE + 139)
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#define CLKID_VDIN_MEAS_SEL (CLKID_BASE + 140)
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#define CLKID_VDIN_MEAS_DIV (CLKID_BASE + 141)
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#define CLKID_VDIN_MEAS (CLKID_BASE + 142)
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#define CLKID_SD_EMMC_C_SEL (CLKID_BASE + 143)
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#define CLKID_SD_EMMC_C_DIV (CLKID_BASE + 144)
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#define CLKID_SD_EMMC_C (CLKID_BASE + 145)
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#define CLKID_SD_EMMC_A_SEL (CLKID_BASE + 146)
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#define CLKID_SD_EMMC_A_DIV (CLKID_BASE + 147)
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#define CLKID_SD_EMMC_A (CLKID_BASE + 148)
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#define CLKID_SD_EMMC_B_SEL (CLKID_BASE + 149)
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#define CLKID_SD_EMMC_B_DIV (CLKID_BASE + 150)
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#define CLKID_SD_EMMC_B (CLKID_BASE + 151)
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#define CLKID_CDAC_SEL (CLKID_BASE + 152)
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#define CLKID_CDAC_DIV (CLKID_BASE + 153)
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#define CLKID_CDAC (CLKID_BASE + 154)
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#define CLKID_SPICC_SEL (CLKID_BASE + 155)
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#define CLKID_SPICC_DIV (CLKID_BASE + 156)
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#define CLKID_SPICC (CLKID_BASE + 157)
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#define CLKID_PWM_A_SEL (CLKID_BASE + 158)
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#define CLKID_PWM_A_DIV (CLKID_BASE + 159)
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#define CLKID_PWM_A (CLKID_BASE + 160)
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#define CLKID_PWM_B_SEL (CLKID_BASE + 161)
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#define CLKID_PWM_B_DIV (CLKID_BASE + 162)
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#define CLKID_PWM_B (CLKID_BASE + 163)
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#define CLKID_PWM_C_SEL (CLKID_BASE + 164)
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#define CLKID_PWM_C_DIV (CLKID_BASE + 165)
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#define CLKID_PWM_C (CLKID_BASE + 166)
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#define CLKID_PWM_D_SEL (CLKID_BASE + 167)
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#define CLKID_PWM_D_DIV (CLKID_BASE + 168)
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#define CLKID_PWM_D (CLKID_BASE + 169)
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#define CLKID_PWM_E_SEL (CLKID_BASE + 170)
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#define CLKID_PWM_E_DIV (CLKID_BASE + 171)
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#define CLKID_PWM_E (CLKID_BASE + 172)
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#define CLKID_PWM_F_SEL (CLKID_BASE + 173)
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#define CLKID_PWM_F_DIV (CLKID_BASE + 174)
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#define CLKID_PWM_F (CLKID_BASE + 175)
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#define CLKID_SAR_ADC_SEL (CLKID_BASE + 176)
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#define CLKID_SAR_ADC_DIV (CLKID_BASE + 177)
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#define CLKID_SAR_ADC (CLKID_BASE + 178)
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#define CLKID_GEN_SEL (CLKID_BASE + 179)
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#define CLKID_GEN_DIV (CLKID_BASE + 180)
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#define CLKID_GEN (CLKID_BASE + 181)
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#define CLKID_SYS_DDR (CLKID_BASE + 182)
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#define CLKID_SYS_DOS (CLKID_BASE + 183)
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#define CLKID_SYS_ETHPHY (CLKID_BASE + 184)
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#define CLKID_SYS_MALI_GATE (CLKID_BASE + 185)
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#define CLKID_SYS_AOCPU (CLKID_BASE + 186)
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#define CLKID_SYS_AUCPU (CLKID_BASE + 187)
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#define CLKID_SYS_CEC (CLKID_BASE + 188)
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#define CLKID_SYS_SD_EMMC_A (CLKID_BASE + 189)
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#define CLKID_SYS_SD_EMMC_B (CLKID_BASE + 190)
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#define CLKID_SYS_SD_EMMC_C (CLKID_BASE + 191)
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#define CLKID_SYS_SMARTCARD (CLKID_BASE + 192)
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#define CLKID_SYS_ACODEC (CLKID_BASE + 193)
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#define CLKID_SYS_MSR_CLK (CLKID_BASE + 194)
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#define CLKID_SYS_IR_CTRL (CLKID_BASE + 195)
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#define CLKID_SYS_AUDIO (CLKID_BASE + 196)
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#define CLKID_SYS_ETH (CLKID_BASE + 197)
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#define CLKID_SYS_UART_A (CLKID_BASE + 198)
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#define CLKID_SYS_UART_B (CLKID_BASE + 199)
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#define CLKID_SYS_UART_C (CLKID_BASE + 200)
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#define CLKID_SYS_UART_D (CLKID_BASE + 201)
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#define CLKID_SYS_UART_E (CLKID_BASE + 202)
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#define CLKID_SYS_TS_PLL (CLKID_BASE + 203)
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#define CLKID_SYS_SPICC0 (CLKID_BASE + 204)
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#define CLKID_SYS_USB (CLKID_BASE + 205)
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#define CLKID_SYS_I2C_M_A (CLKID_BASE + 206)
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#define CLKID_SYS_I2C_M_B (CLKID_BASE + 207)
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#define CLKID_SYS_I2C_M_C (CLKID_BASE + 208)
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#define CLKID_SYS_I2C_M_D (CLKID_BASE + 209)
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#define CLKID_SYS_I2C_M_E (CLKID_BASE + 210)
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#define CLKID_SYS_HDMITX_APB (CLKID_BASE + 211)
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#define CLKID_SYS_I2C_S_A (CLKID_BASE + 212)
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#define CLKID_SYS_HDMI20_AES (CLKID_BASE + 213)
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#define CLKID_SYS_MMC_APB (CLKID_BASE + 214)
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#define CLKID_SYS_CPU_APB (CLKID_BASE + 215)
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#define CLKID_SYS_VPU_INTR (CLKID_BASE + 216)
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#define CLKID_SYS_SAR_ADC (CLKID_BASE + 217)
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#define CLKID_SYS_PWM_J (CLKID_BASE + 218)
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#define CLKID_SYS_GIC (CLKID_BASE + 219)
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#define CLKID_SYS_PWM_I (CLKID_BASE + 220)
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#define CLKID_SYS_PWM_H (CLKID_BASE + 221)
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#define CLKID_SYS_PWM_G (CLKID_BASE + 222)
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#define CLKID_SYS_PWM_F (CLKID_BASE + 223)
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#define CLKID_SYS_PWM_E (CLKID_BASE + 224)
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#define CLKID_SYS_PWM_D (CLKID_BASE + 225)
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#define CLKID_SYS_PWM_C (CLKID_BASE + 226)
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#define CLKID_SYS_PWM_B (CLKID_BASE + 227)
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#define CLKID_SYS_PWM_A (CLKID_BASE + 228)
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#define CLKID_AXI_SYS_NIC (CLKID_BASE + 229)
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#define CLKID_AXI_SRAM (CLKID_BASE + 230)
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#define CLKID_AXI_DEV0_MMC (CLKID_BASE + 231)
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#define NR_CLKS (CLKID_BASE + 232)
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#endif /* __S7_CLKC_H */
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