383 lines
13 KiB
C
383 lines
13 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __G12A_CLKC_H
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#define __G12A_CLKC_H
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#define CLKID_SYS_PLL 0
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#define CLKID_FIXED_PLL 1
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#define CLKID_FCLK_DIV2 2
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#define CLKID_FCLK_DIV3 3
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#define CLKID_FCLK_DIV4 4
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#define CLKID_FCLK_DIV5 5
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#define CLKID_FCLK_DIV7 6
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#define CLKID_GP0_PLL 7
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#define CLKID_MPEG_SEL 8
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#define CLKID_MPEG_DIV 9
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#define CLKID_CLK81 10
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#define CLKID_MPLL0 11
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#define CLKID_MPLL1 12
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#define CLKID_MPLL2 13
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#define CLKID_MPLL3 14
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#define CLKID_DDR 15
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#define CLKID_DOS 16
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#define CLKID_AUDIO_LOCKER 17
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#define CLKID_MIPI_DSI_HOST 18
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#define CLKID_ETH_PHY 19
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#define CLKID_ISA 20
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#define CLKID_PL301 21
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#define CLKID_PERIPHS 22
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#define CLKID_SPICC0 23
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#define CLKID_I2C 24
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#define CLKID_SANA 25
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#define CLKID_SD 26
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#define CLKID_RNG0 27
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#define CLKID_UART0 28
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#define CLKID_SPICC1 29
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#define CLKID_HIU_IFACE 30
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#define CLKID_MIPI_DSI_PHY 31
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#define CLKID_ASSIST_MISC 32
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#define CLKID_SD_EMMC_A 33
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#define CLKID_SD_EMMC_B 34
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#define CLKID_SD_EMMC_C 35
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#define CLKID_AUDIO_CODEC 36
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#define CLKID_AUDIO 37
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#define CLKID_ETH 38
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#define CLKID_DEMUX 39
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#define CLKID_AUDIO_IFIFO 40
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#define CLKID_ADC 41
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#define CLKID_UART1 42
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#define CLKID_GE2D 43
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#define CLKID_RESET 44
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#define CLKID_PCIE_COMB 45
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#define CLKID_PARSER 46
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#define CLKID_USB 47
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#define CLKID_PCIE_PHY 48
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#define CLKID_AHB_ARB0 49
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#define CLKID_AHB_DATA_BUS 50
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#define CLKID_AHB_CTRL_BUS 51
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#define CLKID_HTX_HDCP22 52
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#define CLKID_HTX_PCLK 53
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#define CLKID_BT656 54
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#define CLKID_USB1_DDR_BRIDGE 55
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#define CLKID_MMC_PCLK 56
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#define CLKID_UART2 57
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#define CLKID_VPU_INTR 58
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#define CLKID_GIC 59
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#define CLKID_SD_EMMC_A_CLK0 60
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#define CLKID_SD_EMMC_B_CLK0 61
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#define CLKID_SD_EMMC_C_CLK0 62
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#define CLKID_SD_EMMC_A_CLK0_SEL 63
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#define CLKID_SD_EMMC_A_CLK0_DIV 64
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#define CLKID_SD_EMMC_B_CLK0_SEL 65
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#define CLKID_SD_EMMC_B_CLK0_DIV 66
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#define CLKID_SD_EMMC_C_CLK0_SEL 67
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#define CLKID_SD_EMMC_C_CLK0_DIV 68
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#define CLKID_MPLL0_DIV 69
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#define CLKID_MPLL1_DIV 70
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#define CLKID_MPLL2_DIV 71
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#define CLKID_MPLL3_DIV 72
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#define CLKID_MPLL_PREDIV 73
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#define CLKID_HIFI_PLL 74
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#define CLKID_FCLK_DIV2_DIV 75
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#define CLKID_FCLK_DIV3_DIV 76
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#define CLKID_FCLK_DIV4_DIV 77
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#define CLKID_FCLK_DIV5_DIV 78
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#define CLKID_FCLK_DIV7_DIV 79
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#define CLKID_VCLK2_VENCI0 80
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#define CLKID_VCLK2_VENCI1 81
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#define CLKID_VCLK2_VENCP0 82
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#define CLKID_VCLK2_VENCP1 83
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#define CLKID_VCLK2_VENCT0 84
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#define CLKID_VCLK2_VENCT1 85
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#define CLKID_VCLK2_OTHER 86
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#define CLKID_VCLK2_ENCI 87
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#define CLKID_VCLK2_ENCP 88
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#define CLKID_DAC_CLK 89
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#define CLKID_AOCLK 90
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#define CLKID_IEC958 91
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#define CLKID_ENC480P 92
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#define CLKID_RNG1 93
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#define CLKID_VCLK2_ENCT 94
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#define CLKID_VCLK2_ENCL 95
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#define CLKID_VCLK2_VENCLMMC 96
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#define CLKID_VCLK2_VENCL 97
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#define CLKID_VCLK2_OTHER1 98
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#define CLKID_FCLK_DIV2P5 99
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#define CLKID_FCLK_DIV2P5_DIV 100
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#define CLKID_FIXED_PLL_DCO 101
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#define CLKID_SYS_PLL_DCO 102
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#define CLKID_GP0_PLL_DCO 103
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#define CLKID_HIFI_PLL_DCO 104
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#define CLKID_DMA 105
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#define CLKID_EFUSE 106
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#define CLKID_ROM_BOOT 107
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#define CLKID_RESET_SEC 108
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#define CLKID_SEC_AHB_APB3 109
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#define CLKID_VPU_0_SEL 110
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#define CLKID_VPU_0_DIV 111
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#define CLKID_VPU_0 112
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#define CLKID_VPU_1_SEL 113
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#define CLKID_VPU_1_DIV 114
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#define CLKID_VPU_1 115
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#define CLKID_VPU 116
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#define CLKID_VAPB_0_SEL 117
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#define CLKID_VAPB_0_DIV 118
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#define CLKID_VAPB_0 119
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#define CLKID_VAPB_1_SEL 120
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#define CLKID_VAPB_1_DIV 121
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#define CLKID_VAPB_1 122
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#define CLKID_VAPB_SEL 123
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#define CLKID_GE2D_GATE 124
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#define CLKID_HDMI_PLL_DCO 125
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#define CLKID_HDMI_PLL_OD 126
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#define CLKID_HDMI_PLL_OD2 127
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#define CLKID_HDMI_PLL 128
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#define CLKID_VID_PLL 129
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#define CLKID_VID_PLL_SEL 130
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#define CLKID_VID_PLL_DIV 131
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#define CLKID_VCLK_SEL 132
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#define CLKID_VCLK2_SEL 133
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#define CLKID_VCLK_INPUT 134
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#define CLKID_VCLK2_INPUT 135
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#define CLKID_VCLK_DIV 136
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#define CLKID_VCLK2_DIV 137
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#define CLKID_VCLK 138
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#define CLKID_VCLK2 139
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#define CLKID_VCLK_DIV2_EN 140
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#define CLKID_VCLK_DIV4_EN 141
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#define CLKID_VCLK_DIV6_EN 142
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#define CLKID_VCLK_DIV12_EN 143
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#define CLKID_VCLK2_DIV2_EN 144
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#define CLKID_VCLK2_DIV4_EN 145
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#define CLKID_VCLK2_DIV6_EN 146
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#define CLKID_VCLK2_DIV12_EN 147
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#define CLKID_VCLK_DIV1 148
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#define CLKID_VCLK_DIV2 149
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#define CLKID_VCLK_DIV4 150
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#define CLKID_VCLK_DIV6 151
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#define CLKID_VCLK_DIV12 152
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#define CLKID_VCLK2_DIV1 153
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#define CLKID_VCLK2_DIV2 154
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#define CLKID_VCLK2_DIV4 155
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#define CLKID_VCLK2_DIV6 156
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#define CLKID_VCLK2_DIV12 157
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#define CLKID_CTS_ENCI_SEL 158
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#define CLKID_CTS_ENCP_SEL 159
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#define CLKID_CTS_VDAC_SEL 160
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#define CLKID_HDMI_TX_SEL 161
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#define CLKID_CTS_ENCI 162
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#define CLKID_CTS_ENCP 163
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#define CLKID_CTS_VDAC 164
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#define CLKID_HDMI_TX 165
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#define CLKID_HDMI_SEL 166
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#define CLKID_HDMI_DIV 167
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#define CLKID_HDMI 168
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#define CLKID_MALI_0_SEL 169
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#define CLKID_MALI_0_DIV 170
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#define CLKID_MALI_0 171
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#define CLKID_MALI_1_SEL 172
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#define CLKID_MALI_1_DIV 173
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#define CLKID_MALI_1 174
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#define CLKID_MALI 175
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#define CLKID_MPLL_50M_DIV 176
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#define CLKID_MPLL_50M 177
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#define CLKID_SYS_PLL_DIV16_EN 178
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#define CLKID_SYS_PLL_DIV16 179
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#define CLKID_CPU_CLK_DYN0_SEL 180
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#define CLKID_CPU_CLK_DYN0_DIV 181
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#define CLKID_CPU_CLK_DYN0 182
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#define CLKID_CPU_CLK_DYN1_SEL 183
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#define CLKID_CPU_CLK_DYN1_DIV 184
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#define CLKID_CPU_CLK_DYN1 185
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#define CLKID_CPU_CLK_DYN 186
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#define CLKID_CPU_CLK 187
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#define CLKID_CPU_CLK_DIV16_EN 188
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#define CLKID_CPU_CLK_DIV16 189
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#define CLKID_CPU_CLK_APB_DIV 190
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#define CLKID_CPU_CLK_APB 191
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#define CLKID_CPU_CLK_ATB_DIV 192
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#define CLKID_CPU_CLK_ATB 193
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#define CLKID_CPU_CLK_AXI_DIV 194
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#define CLKID_CPU_CLK_AXI 195
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#define CLKID_CPU_CLK_TRACE_DIV 196
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#define CLKID_CPU_CLK_TRACE 197
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#define CLKID_PCIE_PLL_DCO 198
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#define CLKID_PCIE_PLL_DCO_DIV2 199
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#define CLKID_PCIE_PLL_OD 200
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#define CLKID_PCIE_PLL 201
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#define CLKID_VDEC_P0_SEL 202
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#define CLKID_VDEC_P0_DIV 203
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#define CLKID_VDEC_P0 204
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#define CLKID_HEVC_P0_SEL 205
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#define CLKID_HEVC_P0_DIV 206
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#define CLKID_HEVC_P0 207
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#define CLKID_HEVCF_P0_SEL 208
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#define CLKID_HEVCF_P0_DIV 209
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#define CLKID_HEVCF_P0 210
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#define CLKID_TS_DIV 211
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#define CLKID_TS 212
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#define CLKID_SYS1_PLL_DCO 213
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#define CLKID_SYS1_PLL 214
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#define CLKID_SYS1_PLL_DIV16_EN 215
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#define CLKID_SYS1_PLL_DIV16 216
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#define CLKID_CPUB_CLK_DYN0_SEL 217
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#define CLKID_CPUB_CLK_DYN0_DIV 218
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#define CLKID_CPUB_CLK_DYN0 219
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#define CLKID_CPUB_CLK_DYN1_SEL 220
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#define CLKID_CPUB_CLK_DYN1_DIV 221
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#define CLKID_CPUB_CLK_DYN1 222
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#define CLKID_CPUB_CLK_DYN 223
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#define CLKID_CPUB_CLK 224
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#define CLKID_CPUB_CLK_DIV16_EN 225
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#define CLKID_CPUB_CLK_DIV16 226
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#define CLKID_CPUB_CLK_DIV2 227
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#define CLKID_CPUB_CLK_DIV3 228
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#define CLKID_CPUB_CLK_DIV4 229
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#define CLKID_CPUB_CLK_DIV5 230
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#define CLKID_CPUB_CLK_DIV6 231
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#define CLKID_CPUB_CLK_DIV7 232
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#define CLKID_CPUB_CLK_DIV8 233
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#define CLKID_CPUB_CLK_APB_SEL 234
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#define CLKID_CPUB_CLK_APB 235
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#define CLKID_CPUB_CLK_ATB_SEL 236
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#define CLKID_CPUB_CLK_ATB 237
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#define CLKID_CPUB_CLK_AXI_SEL 238
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#define CLKID_CPUB_CLK_AXI 239
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#define CLKID_CPUB_CLK_TRACE_SEL 240
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#define CLKID_CPUB_CLK_TRACE 241
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#define CLKID_GP1_PLL_DCO 242
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#define CLKID_GP1_PLL 243
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#define CLKID_DSU_CLK_DYN0_SEL 244
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#define CLKID_DSU_CLK_DYN0_DIV 245
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#define CLKID_DSU_CLK_DYN0 246
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#define CLKID_DSU_CLK_DYN1_SEL 247
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#define CLKID_DSU_CLK_DYN1_DIV 248
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#define CLKID_DSU_CLK_DYN1 249
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#define CLKID_DSU_CLK_DYN 250
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#define CLKID_DSU_CLK_FINAL 251
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#define CLKID_DSU_CLK 252
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#define CLKID_CPU1_CLK 253
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#define CLKID_CPU2_CLK 254
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#define CLKID_CPU3_CLK 255
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#define CLKID_PCIE_HCSL 256
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#define CLKID_PCIE_BGP 257
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#define CLKID_25M_CLK_DIV 258
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#define CLKID_25M_CLK_GATE 259
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#define CLKID_24M_CLK_GATE 260
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#define CLKID_12M_CLK_DIV 261
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#define CLKID_12M_CLK_GATE 262
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#define CLKID_GEN_MUX 263
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#define CLKID_GEN_DIV 264
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#define CLKID_GEN 265
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/* Media clocks */
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#define MEDIA_BASE (266 + 0)
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#define CLKID_DSI_MEAS_MUX (MEDIA_BASE + 0)
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#define CLKID_DSI_MEAS_DIV (MEDIA_BASE + 1)
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#define CLKID_DSI_MEAS (MEDIA_BASE + 2)
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#define CLKID_VDEC_P1_MUX (MEDIA_BASE + 3)
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#define CLKID_VDEC_P1_DIV (MEDIA_BASE + 4)
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#define CLKID_VDEC_P1 (MEDIA_BASE + 5)
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#define CLKID_VDEC_MUX (MEDIA_BASE + 6)
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#define CLKID_HCODEC_P0_MUX (MEDIA_BASE + 7)
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#define CLKID_HCODEC_P0_DIV (MEDIA_BASE + 8)
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#define CLKID_HCODEC_P0 (MEDIA_BASE + 9)
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#define CLKID_HCODEC_P1_MUX (MEDIA_BASE + 10)
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#define CLKID_HCODEC_P1_DIV (MEDIA_BASE + 11)
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#define CLKID_HCODEC_P1 (MEDIA_BASE + 12)
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#define CLKID_HCODEC_MUX (MEDIA_BASE + 13)
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#define CLKID_HEVC_P1_MUX (MEDIA_BASE + 14)
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#define CLKID_HEVC_P1_DIV (MEDIA_BASE + 15)
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#define CLKID_HEVC_P1 (MEDIA_BASE + 16)
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#define CLKID_HEVC_MUX (MEDIA_BASE + 17)
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#define CLKID_HEVCF_P1_MUX (MEDIA_BASE + 18)
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#define CLKID_HEVCF_P1_DIV (MEDIA_BASE + 19)
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#define CLKID_HEVCF_P1 (MEDIA_BASE + 20)
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#define CLKID_HEVCF_MUX (MEDIA_BASE + 21)
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#define CLKID_VPU_CLKB_TMP_MUX (MEDIA_BASE + 22)
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#define CLKID_VPU_CLKB_TMP_DIV (MEDIA_BASE + 23)
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#define CLKID_VPU_CLKB_TMP (MEDIA_BASE + 24)
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#define CLKID_VPU_CLKB_DIV (MEDIA_BASE + 25)
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#define CLKID_VPU_CLKB (MEDIA_BASE + 26)
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#define CLKID_VPU_CLKC_P0_MUX (MEDIA_BASE + 27)
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#define CLKID_VPU_CLKC_P0_DIV (MEDIA_BASE + 28)
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#define CLKID_VPU_CLKC_P0 (MEDIA_BASE + 29)
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#define CLKID_VPU_CLKC_P1_MUX (MEDIA_BASE + 30)
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#define CLKID_VPU_CLKC_P1_DIV (MEDIA_BASE + 31)
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#define CLKID_VPU_CLKC_P1 (MEDIA_BASE + 32)
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#define CLKID_VPU_CLKC_MUX (MEDIA_BASE + 33)
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#define CLKID_VDIN_MEAS_MUX (MEDIA_BASE + 34)
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#define CLKID_VDIN_MEAS_DIV (MEDIA_BASE + 35)
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#define CLKID_VDIN_MEAS_GATE (MEDIA_BASE + 36)
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#define CLKID_WAVE_A_SEL (MEDIA_BASE + 37)
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#define CLKID_WAVE_A_DIV (MEDIA_BASE + 38)
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#define CLKID_WAVE_A_CLK (MEDIA_BASE + 39)
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#define CLKID_WAVE_B_SEL (MEDIA_BASE + 40)
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#define CLKID_WAVE_B_DIV (MEDIA_BASE + 41)
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#define CLKID_WAVE_B_CLK (MEDIA_BASE + 42)
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#define CLKID_WAVE_C_SEL (MEDIA_BASE + 43)
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#define CLKID_WAVE_C_DIV (MEDIA_BASE + 44)
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#define CLKID_WAVE_C_CLK (MEDIA_BASE + 45)
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#define CLKID_VIPNANOQ_CORE_MUX (MEDIA_BASE + 46)
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#define CLKID_VIPNANOQ_CORE_DIV (MEDIA_BASE + 47)
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#define CLKID_VIPNANOQ_CORE_GATE (MEDIA_BASE + 48)
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#define CLKID_VIPNANOQ_AXI_MUX (MEDIA_BASE + 49)
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#define CLKID_VIPNANOQ_AXI_DIV (MEDIA_BASE + 50)
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#define CLKID_VIPNANOQ_AXI_GATE (MEDIA_BASE + 51)
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#define CLKID_GDC_CORE_CLK_MUX (MEDIA_BASE + 52)
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#define CLKID_GDC_CORE_CLK_DIV (MEDIA_BASE + 53)
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#define CLKID_GDC_CORE_CLK (MEDIA_BASE + 54)
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#define CLKID_GDC_AXI_CLK_MUX (MEDIA_BASE + 55)
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#define CLKID_GDC_AXI_CLK_DIV (MEDIA_BASE + 56)
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#define CLKID_GDC_AXI_CLK (MEDIA_BASE + 57)
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#define CLKID_MIPI_ISP_CLK_MUX (MEDIA_BASE + 58)
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#define CLKID_MIPI_ISP_CLK_DIV (MEDIA_BASE + 59)
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#define CLKID_MIPI_ISP_CLK (MEDIA_BASE + 60)
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#define CLKID_MIPI_CSI_PHY_CLK0_MUX (MEDIA_BASE + 61)
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#define CLKID_MIPI_CSI_PHY_CLK0_DIV (MEDIA_BASE + 62)
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#define CLKID_MIPI_CSI_PHY_CLK0 (MEDIA_BASE + 63)
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#define CLKID_MIPI_CSI_PHY_CLK1_MUX (MEDIA_BASE + 64)
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#define CLKID_MIPI_CSI_PHY_CLK1_DIV (MEDIA_BASE + 65)
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#define CLKID_MIPI_CSI_PHY_CLK1 (MEDIA_BASE + 66)
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#define CLKID_MIPI_CSI_PHY_CLK (MEDIA_BASE + 67)
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#define CLKID_CSI_ADAPT_CLK_MUX (MEDIA_BASE + 68)
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#define CLKID_CSI_ADAPT_CLK_DIV (MEDIA_BASE + 69)
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#define CLKID_CSI_ADAPT_CLK (MEDIA_BASE + 70)
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/*misc clocks*/
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#define MISC_BASE (MEDIA_BASE + 71)
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#define CLKID_SPICC0_MUX (MISC_BASE + 0)
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#define CLKID_SPICC0_DIV (MISC_BASE + 1)
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#define CLKID_SPICC0_GATE (MISC_BASE + 2)
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#define CLKID_SPICC1_MUX (MISC_BASE + 3)
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#define CLKID_SPICC1_DIV (MISC_BASE + 4)
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#define CLKID_SPICC1_GATE (MISC_BASE + 5)
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#define CLKID_BT656_MUX (MISC_BASE + 6)
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#define CLKID_BT656_DIV (MISC_BASE + 7)
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#define CLKID_BT656_GATE (MISC_BASE + 8)
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/*G12B gate*/
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#define G21B_CLK81 (MISC_BASE + 9)
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#define CLKID_CSI_DIG (G21B_CLK81 + 0)
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#define CLKID_VIPNANOQ (G21B_CLK81 + 1)
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#define CLKID_GDC (G21B_CLK81 + 2)
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#define CLKID_MIPI_ISP (G21B_CLK81 + 3)
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#define CLKID_CSI2_PHY1 (G21B_CLK81 + 4)
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#define CLKID_CSI2_PHY0 (G21B_CLK81 + 5)
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/*sm1 gate*/
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#define SM1_CLK81 (G21B_CLK81 + 6)
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#define CLKID_CSI_PHY (SM1_CLK81 + 0)
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#define CLKID_TEMP_SENSOR (SM1_CLK81 + 1)
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#define CLKID_CSI_ADAPT (SM1_CLK81 + 2)
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#define CLKID_CSI_HOST (SM1_CLK81 + 3)
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#define CLKID_PARSER1 (SM1_CLK81 + 4)
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#define CLKID_NNA (SM1_CLK81 + 5)
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#define CLKID_END (SM1_CLK81 + 6)
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#endif /* __G12A_CLKC_H */
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