740 lines
18 KiB
C
740 lines
18 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/phy/phy.h>
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#include <linux/reset.h>
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#include <linux/platform_device.h>
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#include <linux/bitfield.h>
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#include <dt-bindings/phy/phy.h>
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#include <linux/regmap.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/bits.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_domain.h>
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#include "amlogic-pcie-phy.h"
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static DEFINE_MUTEX(pll_lock);
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static int phy_apb_reset_once;
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static const struct pcie_reset_seq reset_info[] = {
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{ "phy", 10 },
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{ "pipe", 10 },
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{ "mac_apb", 10 },
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{ "por", 10 },
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{ "rst0", 0 },
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{ "rst1", 0 },
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{ "rst2", 0 },
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{ "rst3", 0 },
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{ "rst4", 0 },
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{ "rst5", 0 },
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{ "rst6", 0 },
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{ "rst7", 10 },
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};
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static int amlogic_pcie_phy_a9_power_on(struct amlogic_pcie_phy *pcie_phy)
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{
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return 0;
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}
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static void amlogic_pcie_phy_do_reset(struct amlogic_pcie_phy *pcie_phy, int cnt, u32 flag)
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{
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struct device *dev = pcie_phy->dev;
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u32 reg[2], val;
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int ret = 0;
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ret = of_property_read_u32_array(dev_of_node(dev),
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kasprintf(GFP_KERNEL, "pcie_rst_%d", cnt),
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reg, ARRAY_SIZE(reg));
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if (ret) {
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dev_err(dev, "pcie_rst setting read failed\n");
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return;
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}
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if (flag == 0) {
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val = readl(pcie_phy->reset_base + reg[0]);
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val &= ~(reg[1]);
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writel(val, pcie_phy->reset_base + reg[0]);
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dev_dbg(dev, "assert cnt=%d, reg[0]=0x%x, reg[1]=0x%x\n", cnt, reg[0], reg[1]);
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} else {
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val = readl(pcie_phy->reset_base + reg[0]);
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val |= (reg[1]);
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writel(val, pcie_phy->reset_base + reg[0]);
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dev_dbg(dev, "deassert cnt=%d, reg[0]=0x%x, reg[1]=0x%x\n", cnt, reg[0], reg[1]);
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}
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}
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static int amlogic_pcie_phy_do_phy_apb_reset(struct amlogic_pcie_phy *pcie_phy)
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{
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struct device *dev = pcie_phy->dev;
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u32 reg[2], val;
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int ret = 0;
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ret = of_property_read_u32_array(dev_of_node(dev),
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"pcie-phy-apb-rst",
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reg, ARRAY_SIZE(reg));
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if (ret) {
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dev_err(dev, "failed to request pcie_reset_number\n");
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return ret;
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}
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val = readl(pcie_phy->reset_base + reg[0]);
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val &= ~(reg[1]);
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writel(val, pcie_phy->reset_base + reg[0]);
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usleep_range(20, 30);
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val = readl(pcie_phy->reset_base + reg[0]);
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val |= (reg[1]);
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writel(val, pcie_phy->reset_base + reg[0]);
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usleep_range(20, 30);
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return ret;
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}
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static int amlogic_pcie_phy_apb_reset(struct amlogic_pcie_phy *pcie_phy)
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{
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struct device *dev = pcie_phy->dev;
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int ret;
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bool shared = (pcie_phy->port_num == 0 || pcie_phy->port_num == 1);
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if (pcie_phy->reset_base)
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goto set_rst_reg;
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if (!pcie_phy->phy_apb_rst)
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return 0;
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if (shared && phy_apb_reset_once) {
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dev_info(dev, "phy_apb shared reset already done, skip\n");
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return 0;
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}
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ret = reset_control_deassert(pcie_phy->phy_apb_rst);
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if (ret < 0) {
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dev_err(dev, "deassert phy_apb_rst err %d\n", ret);
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return ret;
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}
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ret = reset_control_assert(pcie_phy->phy_apb_rst);
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if (ret < 0) {
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dev_err(dev, "assert phy_apb_rst err %d\n", ret);
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return ret;
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}
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fsleep(100);
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ret = reset_control_deassert(pcie_phy->phy_apb_rst);
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if (ret < 0) {
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dev_err(dev, "deassert phy_apb_rst err %d\n", ret);
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return ret;
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}
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fsleep(100);
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if (shared) {
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phy_apb_reset_once = 1;
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dev_dbg(dev, "phy_apb shared reset pulse done\n");
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} else {
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dev_dbg(dev, "phy_apb independent reset pulse done\n");
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}
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return 0;
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set_rst_reg:
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if (shared && phy_apb_reset_once)
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return 0;
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ret = amlogic_pcie_phy_do_phy_apb_reset(pcie_phy);
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if (ret)
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return ret;
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if (shared)
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phy_apb_reset_once = 1;
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return 0;
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}
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static int amlogic_pcie_phy_assert_reset(struct amlogic_pcie_phy *pcie_phy)
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{
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struct device *dev = pcie_phy->dev;
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int ret = 0, i;
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if (pcie_phy->reset_base)
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goto set_rst_reg;
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for (i = 0; i < pcie_phy->reset_number; i++) {
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ret = reset_control_assert(pcie_phy->resets[i].rstc);
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if (ret < 0) {
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dev_err(dev, "Failed to assert '%s': %d\n", pcie_phy->resets[i].id, ret);
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return ret;
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}
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}
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return 0;
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set_rst_reg:
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for (i = 1; i <= pcie_phy->reset_number; i++)
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amlogic_pcie_phy_do_reset(pcie_phy, i, 0);
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return 0;
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}
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static int amlogic_pcie_phy_deassert_reset(struct amlogic_pcie_phy *pcie_phy)
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{
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struct device *dev = pcie_phy->dev;
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int ret = 0, i;
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if (pcie_phy->reset_base)
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goto set_rst_reg;
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for (i = 0; i < pcie_phy->reset_number; i++) {
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ret = reset_control_deassert(pcie_phy->resets[i].rstc);
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if (ret < 0) {
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dev_err(dev, "Failed to deassert '%s': %d\n", pcie_phy->resets[i].id, ret);
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return ret;
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}
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if (reset_info[i].delay_us)
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usleep_range(reset_info[i].delay_us, reset_info[i].delay_us + 10);
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}
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return 0;
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set_rst_reg:
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for (i = 1; i <= pcie_phy->reset_number; i++)
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amlogic_pcie_phy_do_reset(pcie_phy, i, 1);
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return 0;
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}
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static int amlogic_pcie_phy_do_pll_set(struct amlogic_pcie_phy *pcie_phy, int cnt)
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{
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struct device *dev = pcie_phy->dev;
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u32 reg[2], val;
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int ret;
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ret = of_property_read_u32_array(dev_of_node(dev),
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kasprintf(GFP_KERNEL, "phy_pll_setting_%d", cnt),
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reg, ARRAY_SIZE(reg));
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if (ret) {
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dev_err(dev, "amlogic phy pll setting read failed\n");
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return ret;
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}
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if (reg[0] != 0x017c && reg[0] != 0x117c) {
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ret = regmap_write(pcie_phy->regmap, reg[0], reg[1]);
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if (ret)
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return ret;
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fsleep(100);
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} else {
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ret = regmap_read_poll_timeout(pcie_phy->regmap, reg[0], val,
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((val & reg[1]) == reg[1]), 200, 500000);
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if (ret)
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dev_err(dev, "aml pcie phy pll lock failed val = 0x%x\n", val);
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else
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dev_dbg(dev, "aml pcie phy pll locked\n");
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}
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dev_dbg(dev, "aml pcie phy pll cnt=%d, reg[0]=0x%x, reg[1]=0x%x\n", cnt, reg[0], reg[1]);
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return ret;
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}
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static int amlogic_pcie_phy_configure_pll(struct amlogic_pcie_phy *pcie_phy)
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{
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struct device *dev = pcie_phy->dev;
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struct device_node *np = dev->of_node;
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u32 groups[32], val;
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int num_groups, ret, i, g;
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mutex_lock(&pll_lock);
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num_groups = of_property_count_u32_elems(np, "pll_groups");
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if (num_groups <= 0) {
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dev_err(dev, "Missing pll_groups property\n");
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ret = -EINVAL;
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goto unlock;
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}
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ret = of_property_read_u32_array(np, "pll_groups", groups, num_groups);
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if (ret) {
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dev_err(dev, "Failed to read pll_groups\n");
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ret = -EINVAL;
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goto unlock;
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}
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for (g = 0; g < num_groups / 5; g++) {
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int group_id = groups[g * 5];
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u32 lock_reg = groups[g * 5 + 1];
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u32 lock_mask = groups[g * 5 + 2];
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int start = groups[g * 5 + 3];
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int end = groups[g * 5 + 4];
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bool locked = false;
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dev_dbg(dev,
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"PHY%d: configuring PLL%d (settings %d-%d) reg=0x%x, mask=0x%x\n",
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pcie_phy->port_num, group_id, start, end, lock_reg, lock_mask);
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ret = regmap_read(pcie_phy->regmap, lock_reg, &val);
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if (!ret && ((val & lock_mask) == lock_mask)) {
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locked = true;
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dev_dbg(dev, "PHY%d: PLL%d already locked\n",
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pcie_phy->port_num, group_id);
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continue;
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}
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for (i = start; i <= end && i <= pcie_phy->pll_setting_number; i++) {
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ret = amlogic_pcie_phy_do_pll_set(pcie_phy, i);
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if (ret) {
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dev_err(dev, "PHY%d PLL%d setting %d failed\n",
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pcie_phy->port_num, group_id, i);
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goto unlock;
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}
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}
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dev_info(dev, "PHY%d: PLL%d locked\n", pcie_phy->port_num, group_id);
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}
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unlock:
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mutex_unlock(&pll_lock);
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return ret;
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}
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static int amlogic_pcie_phy_a9_init(struct amlogic_pcie_phy *pcie_phy)
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{
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struct device *dev = pcie_phy->dev;
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struct device_node *node = dev->of_node;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *efuse_res;
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void __iomem *efuse_base = NULL;
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u32 val, offset = 0;
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int ret = 0;
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ret = clk_prepare_enable(pcie_phy->pcie_phy_clk);
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if (ret) {
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dev_err(dev, "unable to enable pcie_phy clock\n");
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return ret;
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}
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ret = clk_prepare_enable(pcie_phy->pcie_apb_bus_clk);
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if (ret) {
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dev_err(dev, "unable to enable pcie_apb_bus clock\n");
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goto err_pcie_phy_clk;
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}
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ret = pm_runtime_get_sync(pcie_phy->dev);
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if (ret < 0)
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return ret;
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ret = amlogic_pcie_phy_apb_reset(pcie_phy);
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if (ret)
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goto err_phy_cfg;
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ret = amlogic_pcie_phy_assert_reset(pcie_phy);
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if (ret)
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goto err_phy_cfg;
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ret = amlogic_pcie_phy_deassert_reset(pcie_phy);
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if (ret)
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goto err_phy_cfg;
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/* phy init */
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if (pcie_phy->num_lanes == 1) {
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/* set x1 */
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ret = regmap_update_bits(pcie_phy->regmap, 0x0, BIT(0), 1);
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if (ret)
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goto err_phy_cfg;
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/* close fast_sim */
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ret = regmap_update_bits(pcie_phy->regmap, 0x1b8, BIT(21), 0);
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if (ret)
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goto err_phy_cfg;
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/* phy1 and controller B */
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if (pcie_phy->port_num == 1) {
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ret = regmap_update_bits(pcie_phy->regmap, 0x1000, BIT(0), 1);
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if (ret)
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goto err_phy_cfg;
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/* phy1 equalization settings */
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ret = regmap_update_bits(pcie_phy->regmap, 0x1050, GENMASK(9, 5), 0);
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if (ret)
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goto err_phy_cfg;
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ret = regmap_write(pcie_phy->regmap, 0x1084, 0xFF951071);
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if (ret)
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goto err_phy_cfg;
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/* set sqh */
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ret = regmap_write(pcie_phy->regmap, 0x1064, 0x7200);
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if (ret)
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goto err_phy_cfg;
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ret = regmap_update_bits(pcie_phy->regmap, 0x105c, BIT(20), 1);
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if (ret)
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goto err_phy_cfg;
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ret = regmap_update_bits(pcie_phy->regmap, 0x1054, BIT(5), 1);
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if (ret)
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goto err_phy_cfg;
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ret = regmap_update_bits(pcie_phy->regmap, 0x105c, BIT(20), 0);
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if (ret)
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goto err_phy_cfg;
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}
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} else {
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ret = regmap_write(pcie_phy->regmap, 0x84, 0xFF951071);
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if (ret)
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goto err_phy_cfg;
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}
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if (pcie_phy->port_num != 1) {
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/* phy0, 2 set eq */
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ret = regmap_update_bits(pcie_phy->regmap, 0x50, GENMASK(9, 5), 0);
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if (ret)
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goto err_phy_cfg;
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/* set sqh */
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ret = regmap_write(pcie_phy->regmap, 0x64, 0x7200);
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if (ret)
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goto err_phy_cfg;
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ret = regmap_update_bits(pcie_phy->regmap, 0x5c, BIT(20), 1);
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if (ret)
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goto err_phy_cfg;
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ret = regmap_update_bits(pcie_phy->regmap, 0x54, BIT(5), 1);
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if (ret)
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goto err_phy_cfg;
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ret = regmap_update_bits(pcie_phy->regmap, 0x5c, BIT(20), 0);
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if (ret)
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goto err_phy_cfg;
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}
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if (pcie_phy->num_lanes == 1 && pcie_phy->port_num == 2) {
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void __iomem *comb_phy_base;
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comb_phy_base = ioremap(0xfe0086e0, 0x4);
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/* [00]=hsgmi [01]=pcie2 [10]=usb3 [11]=usb3 */
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writel(0x1, comb_phy_base);
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dev_dbg(dev, "PCIe comb phy sel =0x%x\n", readl(comb_phy_base));
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/* phy2 close gen1 dfe */
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ret = regmap_write(pcie_phy->regmap, 0x90, 0x54154268);
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if (ret)
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goto err_phy_cfg;
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/* phy2 close gen2 dfe */
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ret = regmap_write(pcie_phy->regmap, 0x94, 0x54144268);
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if (ret)
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goto err_phy_cfg;
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}
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efuse_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "efuse");
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if (efuse_res) {
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efuse_base = devm_ioremap(dev, efuse_res->start, resource_size(efuse_res));
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if (IS_ERR(efuse_base)) {
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dev_err(dev, "failed to request efuse_base\n");
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ret = PTR_ERR(efuse_base);
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goto err_phy_cfg;
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}
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} else {
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dev_err(dev, "failed to get efuse_base resource\n");
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ret = -ENODEV;
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goto err_phy_cfg;
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}
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if (efuse_base) {
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val = readl(efuse_base);
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dev_dbg(dev, "efuse val = 0x%x\n", val);
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dev_dbg(dev, "boost = 0x%x\n", (u32)((val & GENMASK(11, 7)) >> 7));
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if (pcie_phy->num_lanes == 1 && pcie_phy->port_num == 2) {
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dev_dbg(dev, "pdio = 0x%x\n", (u32)(val & GENMASK(2, 0)));
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dev_dbg(dev, "puio = 0x%x\n", (u32)((val & GENMASK(5, 3)) >> 3));
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dev_dbg(dev, "dcha = 0x%x\n", (u32)((val & GENMASK(16, 13)) >> 13));
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/* boost */
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if (val & BIT(12)) {
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ret = regmap_update_bits(pcie_phy->regmap,
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0x3c, GENMASK(20, 16),
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((val & GENMASK(11, 7)) >> 7));
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if (ret)
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goto err_phy_cfg;
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}
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if (val & BIT(6)) {
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/* puio */
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ret = regmap_update_bits(pcie_phy->regmap,
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0x3c, GENMASK(14, 12),
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((val & GENMASK(5, 3)) >> 3));
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if (ret)
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goto err_phy_cfg;
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/* pdio */
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ret = regmap_update_bits(pcie_phy->regmap,
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0x3c, GENMASK(10, 8),
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val & GENMASK(2, 0));
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if (ret)
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goto err_phy_cfg;
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}
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/* dcha */
|
|
if (val & BIT(17)) {
|
|
ret = regmap_update_bits(pcie_phy->regmap,
|
|
0x7c, GENMASK(7, 4),
|
|
((val & GENMASK(16, 13)) >> 13));
|
|
if (ret)
|
|
goto err_phy_cfg;
|
|
|
|
ret = regmap_update_bits(pcie_phy->regmap,
|
|
0x80, GENMASK(7, 4),
|
|
((val & GENMASK(16, 13)) >> 13));
|
|
if (ret)
|
|
goto err_phy_cfg;
|
|
}
|
|
} else {
|
|
dev_dbg(dev, "u3 tx = 0x%x\n", (u32)((val & GENMASK(21, 18)) >> 18));
|
|
dev_dbg(dev, "u3 rx = 0x%x\n", (u32)((val & GENMASK(26, 23)) >> 23));
|
|
|
|
if (pcie_phy->port_num == 1)
|
|
offset = 0x1000;
|
|
|
|
/* boost */
|
|
if (val & BIT(12)) {
|
|
ret = regmap_update_bits(pcie_phy->regmap,
|
|
0x44 + offset, GENMASK(24, 20),
|
|
((val & GENMASK(11, 7)) >> 7));
|
|
if (ret)
|
|
goto err_phy_cfg;
|
|
}
|
|
|
|
/* TX */
|
|
if (val & BIT(22)) {
|
|
ret = regmap_update_bits(pcie_phy->regmap,
|
|
0x44 + offset, GENMASK(31, 28),
|
|
((val & GENMASK(21, 18)) >> 18));
|
|
if (ret)
|
|
goto err_phy_cfg;
|
|
}
|
|
|
|
/* RX */
|
|
if (val & BIT(27)) {
|
|
ret = regmap_update_bits(pcie_phy->regmap,
|
|
0x7c + offset, GENMASK(7, 4),
|
|
((val & GENMASK(26, 23)) >> 23));
|
|
if (ret)
|
|
goto err_phy_cfg;
|
|
|
|
ret = regmap_update_bits(pcie_phy->regmap,
|
|
0x80 + offset, GENMASK(7, 4),
|
|
((val & GENMASK(26, 23)) >> 23));
|
|
if (ret)
|
|
goto err_phy_cfg;
|
|
|
|
ret = regmap_update_bits(pcie_phy->regmap,
|
|
0x84 + offset, GENMASK(7, 4),
|
|
((val & GENMASK(26, 23)) >> 23));
|
|
if (ret)
|
|
goto err_phy_cfg;
|
|
}
|
|
}
|
|
}
|
|
|
|
ret = of_property_read_u32(node, "pll_setting_number", &pcie_phy->pll_setting_number);
|
|
if (ret)
|
|
goto err_phy_cfg;
|
|
|
|
ret = amlogic_pcie_phy_configure_pll(pcie_phy);
|
|
if (ret)
|
|
goto err_phy_cfg;
|
|
|
|
return 0;
|
|
|
|
err_phy_cfg:
|
|
if (__clk_is_enabled(pcie_phy->pcie_phy_clk))
|
|
clk_disable_unprepare(pcie_phy->pcie_phy_clk);
|
|
if (__clk_is_enabled(pcie_phy->pcie_apb_bus_clk))
|
|
clk_disable_unprepare(pcie_phy->pcie_apb_bus_clk);
|
|
return ret;
|
|
|
|
err_pcie_phy_clk:
|
|
clk_disable_unprepare(pcie_phy->pcie_phy_clk);
|
|
return ret;
|
|
}
|
|
|
|
static int amlogic_pcie_phy_a9_power_off(struct amlogic_pcie_phy *pcie_phy)
|
|
{
|
|
int ret;
|
|
|
|
if (__clk_is_enabled(pcie_phy->pcie_phy_clk))
|
|
clk_disable_unprepare(pcie_phy->pcie_phy_clk);
|
|
if (__clk_is_enabled(pcie_phy->pcie_apb_bus_clk))
|
|
clk_disable_unprepare(pcie_phy->pcie_apb_bus_clk);
|
|
|
|
ret = pm_runtime_put_sync(pcie_phy->dev);
|
|
if (ret < 0)
|
|
dev_err(pcie_phy->dev, "pm_runtime_put_sync failed\n");
|
|
|
|
if (pcie_phy->port_num == 0 || pcie_phy->port_num == 1)
|
|
phy_apb_reset_once = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amlogic_pcie_phy_a9_exit(struct amlogic_pcie_phy *pcie_phy)
|
|
{
|
|
return amlogic_pcie_phy_a9_power_off(pcie_phy);
|
|
}
|
|
|
|
static int amlogic_pcie_phy_a9_reset(struct amlogic_pcie_phy *pcie_phy)
|
|
{
|
|
int ret;
|
|
|
|
ret = amlogic_pcie_phy_assert_reset(pcie_phy);
|
|
if (ret)
|
|
return ret;
|
|
|
|
usleep_range(100, 150);
|
|
|
|
ret = amlogic_pcie_phy_deassert_reset(pcie_phy);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amlogic_pcie_phy_get_reset(struct amlogic_pcie_phy *pcie_phy)
|
|
{
|
|
struct device *dev = pcie_phy->dev;
|
|
struct device_node *node = dev->of_node;
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct resource *res;
|
|
int ret = 0, i;
|
|
|
|
pcie_phy->phy_apb_rst = devm_reset_control_get_shared(dev, "phy_apb");
|
|
if (IS_ERR(pcie_phy->phy_apb_rst)) {
|
|
if (PTR_ERR(pcie_phy->phy_apb_rst) != -EPROBE_DEFER)
|
|
pcie_phy->phy_apb_rst = NULL;
|
|
goto get_rst_reg;
|
|
}
|
|
|
|
pcie_phy->reset_number = ARRAY_SIZE(reset_info);
|
|
pcie_phy->resets = devm_kcalloc(dev, pcie_phy->reset_number, sizeof(*pcie_phy->resets),
|
|
GFP_KERNEL);
|
|
if (IS_ERR_OR_NULL(pcie_phy->resets))
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < pcie_phy->reset_number; i++)
|
|
pcie_phy->resets[i].id = reset_info[i].name;
|
|
|
|
ret = devm_reset_control_bulk_get_exclusive(dev,
|
|
pcie_phy->reset_number,
|
|
pcie_phy->resets);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "Failed to get resets\n");
|
|
|
|
return 0;
|
|
|
|
get_rst_reg:
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reset");
|
|
if (res) {
|
|
pcie_phy->reset_base = devm_ioremap(dev, res->start, resource_size(res));
|
|
if (IS_ERR(pcie_phy->reset_base)) {
|
|
dev_err(dev, "failed to request reset_base\n");
|
|
return PTR_ERR(pcie_phy->reset_base);
|
|
}
|
|
} else {
|
|
dev_err(dev, "failed to get reset_base resource\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = of_property_read_u32(node, "pcie_rst_number",
|
|
&pcie_phy->reset_number);
|
|
if (ret) {
|
|
dev_err(dev, "failed to request pcie_reset_number\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amlogic_pcie_phy_a9_parse_dt(struct amlogic_pcie_phy *pcie_phy)
|
|
{
|
|
struct device *dev = pcie_phy->dev;
|
|
struct device_node *node = dev->of_node;
|
|
int ret = 0;
|
|
|
|
pcie_phy->pcie_phy_clk = devm_clk_get(dev, "pcie_phy");
|
|
if (IS_ERR(pcie_phy->pcie_phy_clk))
|
|
return dev_err_probe(dev, PTR_ERR(pcie_phy->pcie_phy_clk),
|
|
"pcie_phy_clk clock missing\n");
|
|
|
|
pcie_phy->pcie_apb_bus_clk = devm_clk_get(dev, "pcie_apb_bus");
|
|
if (IS_ERR(pcie_phy->pcie_apb_bus_clk))
|
|
return dev_err_probe(dev, PTR_ERR(pcie_phy->pcie_apb_bus_clk),
|
|
"pcie_apb_bus_clk clock missing\n");
|
|
|
|
ret = amlogic_pcie_phy_get_reset(pcie_phy);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (of_property_read_u32(node, "num-lanes", &pcie_phy->num_lanes)) {
|
|
dev_err(dev, "failed to get num-lanes\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = of_property_read_u32(node, "port-num", &pcie_phy->port_num);
|
|
if (ret) {
|
|
dev_err(dev, "failed to get port-num\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct amlogic_pcie_phy_data pcie_phy_a9_data = {
|
|
.phy_init = amlogic_pcie_phy_a9_init,
|
|
.phy_exit = amlogic_pcie_phy_a9_exit,
|
|
.phy_power_on = amlogic_pcie_phy_a9_power_on,
|
|
.phy_power_off = amlogic_pcie_phy_a9_power_off,
|
|
.phy_reset = amlogic_pcie_phy_a9_reset,
|
|
.parse_dt = amlogic_pcie_phy_a9_parse_dt,
|
|
};
|
|
|
|
static const struct of_device_id pcie_phy_a9_of_match[] = {
|
|
{
|
|
.compatible = "amlogic,a9-pcie-phy",
|
|
.data = &pcie_phy_a9_data,
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, pcie_phy_a9_of_match);
|
|
|
|
static struct platform_driver pcie_phy_a9_driver = {
|
|
.probe = amlogic_pcie_phy_probe,
|
|
.driver = {
|
|
.name = "pcie-phy-a9",
|
|
.of_match_table = pcie_phy_a9_of_match,
|
|
},
|
|
};
|
|
|
|
int __init aml_pcie_phy_a9_init(void)
|
|
{
|
|
return platform_driver_register(&pcie_phy_a9_driver);
|
|
}
|
|
|
|
void __exit aml_pcie_phy_a9_exit(void)
|
|
{
|
|
phy_apb_reset_once = 0;
|
|
|
|
platform_driver_unregister(&pcie_phy_a9_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR("Amlogic Inc");
|
|
MODULE_DESCRIPTION("Amlogic PCIE PHY driver");
|
|
MODULE_LICENSE("GPL v2");
|