931 lines
22 KiB
C
931 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* I2C bus driver for Amlogic Meson SoCs
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*
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* Copyright (C) 2014 Beniamino Galvani <[email protected]>
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#ifdef CONFIG_AMLOGIC_MODIFY
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#include <linux/pm_runtime.h>
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#include <linux/pm_domain.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/amlogic/arm-smccc.h>
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#include <linux/amlogic/secure_pwm_i2c.h>
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#include <dt-bindings/i2c/i2c-meson.h>
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#include <linux/delay.h>
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#endif
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/* Meson I2C register map */
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#define REG_CTRL 0x00
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#define REG_SLAVE_ADDR 0x04
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#define REG_TOK_LIST0 0x08
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#define REG_TOK_LIST1 0x0c
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#define REG_TOK_WDATA0 0x10
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#define REG_TOK_WDATA1 0x14
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#define REG_TOK_RDATA0 0x18
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#define REG_TOK_RDATA1 0x1c
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/* Control register fields */
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#define REG_CTRL_START BIT(0)
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#define REG_CTRL_ACK_IGNORE BIT(1)
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#define REG_CTRL_STATUS BIT(2)
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#define REG_CTRL_ERROR BIT(3)
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#define REG_SCL_LEVEL BIT(25)
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#define REG_SDA_LEVEL BIT(26)
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#define REG_CTRL_CLKDIV_SHIFT 12
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#define REG_CTRL_CLKDIV_MASK GENMASK(21, 12)
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#define REG_CTRL_CLKDIVEXT_SHIFT 28
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#define REG_CTRL_CLKDIVEXT_MASK GENMASK(29, 28)
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#ifdef CONFIG_AMLOGIC_MODIFY
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/* keep the same with I2C_TIMEOUT_MS */
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#define MESON_I2C_PM_TIMEOUT 500
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#define DIV_FACTOR 3
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#define DELAY_ADJUST 15
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#endif
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#define I2C_TIMEOUT_MS 500
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enum {
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TOKEN_END = 0,
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TOKEN_START,
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TOKEN_SLAVE_ADDR_WRITE,
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TOKEN_SLAVE_ADDR_READ,
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TOKEN_DATA,
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TOKEN_DATA_LAST,
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TOKEN_STOP,
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};
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enum {
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STATE_IDLE,
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STATE_READ,
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STATE_WRITE,
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};
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struct meson_i2c_data {
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bool tee;
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u32 tee_id;
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};
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/**
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* struct meson_i2c - Meson I2C device private data
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*
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* @adap: I2C adapter instance
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* @dev: Pointer to device structure
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* @regs: Base address of the device memory mapped registers
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* @clk: Pointer to clock structure
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* @msg: Pointer to the current I2C message
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* @state: Current state in the driver state machine
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* @last: Flag set for the last message in the transfer
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* @count: Number of bytes to be sent/received in current transfer
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* @pos: Current position in the send/receive buffer
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* @error: Flag set when an error is received
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* @lock: To avoid race conditions between irq handler and xfer code
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* @done: Completion used to wait for transfer termination
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* @frequency: Operating frequency of I2C bus clock
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* @tokens: Sequence of tokens to be written to the device
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* @num_tokens: Number of tokens
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* @data: Pointer to the controller's platform data
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*/
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struct meson_i2c {
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struct i2c_adapter adap;
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struct device *dev;
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void __iomem *regs;
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struct clk *clk;
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struct i2c_msg *msg;
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int state;
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bool last;
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int count;
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int pos;
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int error;
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spinlock_t lock; //protection for i2c controller critical section
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struct completion done;
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u32 tokens[2];
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int num_tokens;
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#ifdef CONFIG_AMLOGIC_MODIFY
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unsigned long clk_rate;
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unsigned int frequency;
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int retain_fastmode;
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int irq;
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bool is_runtime_sleep;
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#endif
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struct meson_i2c_data *data;
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int mode;
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};
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static void meson_i2c_writel(struct meson_i2c *i2c, u32 data, int reg)
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{
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struct arm_smccc_res res;
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if (i2c->data->tee)
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arm_smccc_smc(SECURE_PWM_I2C, SECID_I2C, i2c->data->tee_id,
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reg, data, 0, 0, 0, &res);
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else
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writel(data, i2c->regs + reg);
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}
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static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
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u32 val)
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{
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u32 data;
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data = readl(i2c->regs + reg);
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data &= ~mask;
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data |= val & mask;
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meson_i2c_writel(i2c, data, reg);
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}
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static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
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{
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i2c->tokens[0] = 0;
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i2c->tokens[1] = 0;
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i2c->num_tokens = 0;
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}
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static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
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{
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if (i2c->num_tokens < 8)
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i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4);
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else
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i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4);
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i2c->num_tokens++;
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}
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#ifdef CONFIG_AMLOGIC_MODIFY
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/*
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* Count = clk/freq = H + L
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* Duty = H/(H + L) = 1/2 -- duty 50%, H/L = 1/1
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* H = n + delay
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* L = 2m
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*
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* =>
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*
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* n = Count/2 - delay
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* m = Count/4
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* Standard Mode : 100k
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*/
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static void meson_i2c_set_clk_div_std(struct meson_i2c *i2c)
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{
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unsigned long clk_rate = i2c->clk_rate;
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unsigned int div_h, div_l;
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unsigned int div_temp;
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div_temp = DIV_ROUND_UP(clk_rate, i2c->frequency);
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div_h = DIV_ROUND_UP(div_temp, 2) - DELAY_ADJUST;
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div_l = DIV_ROUND_UP(div_temp, 4);
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/* clock divider has 12 bits */
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if (div_h >= (1 << 12)) {
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dev_err(i2c->dev, "requested bus frequency too low\n");
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div_h = (1 << 12) - 1;
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}
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if (div_l >= (1 << 12)) {
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dev_err(i2c->dev, "requested bus frequency too low\n");
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div_l = (1 << 12) - 1;
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}
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/*control reg:12-21 bits*/
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meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
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(div_h & GENMASK(9, 0)) << REG_CTRL_CLKDIV_SHIFT);
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meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
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(div_h >> 10) << REG_CTRL_CLKDIVEXT_SHIFT);
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/* set SCL low delay */
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meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, GENMASK(27, 16),
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(div_l << 16) & GENMASK(27, 16));
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/* enable to control SCL low time */
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meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, BIT(28), BIT(28));
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dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div_h %u, div_l %u\n",
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__func__, clk_rate, i2c->frequency, div_h, div_l);
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}
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/*
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* According to I2C-BUS Spec 2.1, in FAST-MODE, LOW period should be at
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* least 1.3uS, and HIGH period should be at lease 0.6. HIGH to LOW
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* ratio as 2 to 5 is more safe.
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* Duty = H/(H + L) = 2/5 -- duty 40%% H/L = 2/3
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* Fast Mode : 400k
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* High Mode : 3400k
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*/
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static void meson_i2c_set_clk_div_fast(struct meson_i2c *i2c)
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{
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unsigned long clk_rate = i2c->clk_rate;
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unsigned int div_h, div_l;
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unsigned int div_temp;
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div_temp = DIV_ROUND_UP(clk_rate * 2, i2c->frequency * 5);
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div_h = div_temp - DELAY_ADJUST;
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div_l = DIV_ROUND_UP(clk_rate * 3, i2c->frequency * 10);
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/* clock divider has 12 bits */
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if (div_h >= (1 << 12)) {
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dev_err(i2c->dev, "requested bus frequency too low\n");
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div_h = (1 << 12) - 1;
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}
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if (div_l >= (1 << 12)) {
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dev_err(i2c->dev, "requested bus frequency too low\n");
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div_l = (1 << 12) - 1;
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}
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/*control reg:12-21 bits*/
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meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
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(div_h & GENMASK(9, 0)) << REG_CTRL_CLKDIV_SHIFT);
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meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
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(div_h >> 10) << REG_CTRL_CLKDIVEXT_SHIFT);
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/* set SCL low delay */
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meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, GENMASK(27, 16),
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(div_l << 16) & GENMASK(27, 16));
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/* enable to control SCL low time */
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meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, BIT(28), BIT(28));
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dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div_h %u, div_l %u\n",
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__func__, clk_rate, i2c->frequency, div_h, div_l);
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}
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static void meson_i2c_set_clk_div(struct meson_i2c *i2c)
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{
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if (i2c->frequency >= 400000) {
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meson_i2c_set_clk_div_fast(i2c);
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} else {
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if (!i2c->retain_fastmode)
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meson_i2c_set_clk_div_std(i2c);
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else
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meson_i2c_set_clk_div_fast(i2c);
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}
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}
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#else
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static void meson_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
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{
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unsigned long clk_rate = clk_get_rate(i2c->clk);
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unsigned int div;
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div = DIV_ROUND_UP(clk_rate, freq * DIV_FACTOR);
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/* clock divider has 12 bits */
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if (div >= (1 << 12)) {
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dev_err(i2c->dev, "requested bus frequency too low\n");
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div = (1 << 12) - 1;
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}
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meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
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(div & GENMASK(9, 0)) << REG_CTRL_CLKDIV_SHIFT);
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meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
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(div >> 10) << REG_CTRL_CLKDIVEXT_SHIFT);
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dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__,
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clk_rate, freq, div);
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}
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#endif
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static void meson_i2c_get_data(struct meson_i2c *i2c, char *buf, int len)
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{
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u32 rdata0, rdata1;
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int i;
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rdata0 = readl(i2c->regs + REG_TOK_RDATA0);
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rdata1 = readl(i2c->regs + REG_TOK_RDATA1);
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dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
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rdata0, rdata1, len);
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for (i = 0; i < min(4, len); i++)
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*buf++ = (rdata0 >> i * 8) & 0xff;
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for (i = 4; i < min(8, len); i++)
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*buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
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}
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static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len)
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{
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u32 wdata0 = 0, wdata1 = 0;
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int i;
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for (i = 0; i < min(4, len); i++)
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wdata0 |= *buf++ << (i * 8);
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for (i = 4; i < min(8, len); i++)
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wdata1 |= *buf++ << ((i - 4) * 8);
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meson_i2c_writel(i2c, wdata0, REG_TOK_WDATA0);
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meson_i2c_writel(i2c, wdata1, REG_TOK_WDATA1);
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dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
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wdata0, wdata1, len);
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}
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static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
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{
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bool write = !(i2c->msg->flags & I2C_M_RD);
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int i;
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i2c->count = min(i2c->msg->len - i2c->pos, 8);
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for (i = 0; i < i2c->count - 1; i++)
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meson_i2c_add_token(i2c, TOKEN_DATA);
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if (i2c->count) {
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if (write || i2c->pos + i2c->count < i2c->msg->len)
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meson_i2c_add_token(i2c, TOKEN_DATA);
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else
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meson_i2c_add_token(i2c, TOKEN_DATA_LAST);
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}
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if (write)
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meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
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if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len)
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meson_i2c_add_token(i2c, TOKEN_STOP);
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meson_i2c_writel(i2c, i2c->tokens[0], REG_TOK_LIST0);
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meson_i2c_writel(i2c, i2c->tokens[1], REG_TOK_LIST1);
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}
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static irqreturn_t meson_i2c_irq(int irqno, void *dev_id)
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{
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struct meson_i2c *i2c = dev_id;
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unsigned int ctrl;
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spin_lock(&i2c->lock);
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meson_i2c_reset_tokens(i2c);
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meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
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ctrl = readl(i2c->regs + REG_CTRL);
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dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n",
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i2c->state, i2c->pos, i2c->count, ctrl);
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if (i2c->state == STATE_IDLE) {
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spin_unlock(&i2c->lock);
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return IRQ_NONE;
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}
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if (ctrl & REG_CTRL_ERROR) {
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/*
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* The bit is set when the IGNORE_NAK bit is cleared
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* and the device didn't respond. In this case, the
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* I2C controller automatically generates a STOP
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* condition.
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*/
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dev_dbg(i2c->dev, "error bit set\n");
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i2c->error = -ENXIO;
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i2c->state = STATE_IDLE;
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complete(&i2c->done);
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goto out;
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}
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if (i2c->state == STATE_READ && i2c->count)
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meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
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i2c->pos += i2c->count;
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if (i2c->pos >= i2c->msg->len) {
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i2c->state = STATE_IDLE;
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complete(&i2c->done);
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goto out;
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}
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/* Restart the processing */
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meson_i2c_prepare_xfer(i2c);
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meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
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out:
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spin_unlock(&i2c->lock);
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return IRQ_HANDLED;
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}
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static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
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{
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int token;
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token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ :
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TOKEN_SLAVE_ADDR_WRITE;
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#ifdef CONFIG_AMLOGIC_MODIFY
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meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, GENMASK(7, 0),
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(unsigned int)((msg->addr << 1) & GENMASK(7, 0)));
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#else
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meson_i2c_writel(i2c, msg->addr << 1, REG_SLAVE_ADDR);
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#endif
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meson_i2c_add_token(i2c, TOKEN_START);
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meson_i2c_add_token(i2c, token);
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}
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static int meson_i2c_xfer_polling_msg(struct meson_i2c *i2c,
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struct i2c_msg *msg, int last)
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{
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unsigned int cnt = 0;
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dev_dbg(i2c->dev, "meson i2c: %s addr 0x%x len %u\n",
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(msg->flags & I2C_M_RD) ? "read" : "write",
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msg->addr, msg->len);
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i2c->msg = msg;
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i2c->last = last;
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i2c->pos = 0;
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i2c->count = 0;
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if ((readl(i2c->regs + REG_CTRL) & REG_SCL_LEVEL) == 0 &&
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(readl(i2c->regs + REG_CTRL) & REG_SDA_LEVEL) == 0) {
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/*
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* I2C bus is error
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*/
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dev_dbg(i2c->dev, "I2C BUS is Error, No pull up register\n");
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return -ENXIO;
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}
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meson_i2c_reset_tokens(i2c);
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meson_i2c_do_start(i2c, msg);
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do {
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meson_i2c_prepare_xfer(i2c);
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if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len)
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meson_i2c_add_token(i2c, TOKEN_STOP);
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/* start the transfer */
|
|
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START,
|
|
REG_CTRL_START);
|
|
while (readl(i2c->regs + REG_CTRL) & REG_CTRL_STATUS) {
|
|
if (cnt > I2C_TIMEOUT_MS * 1000) {
|
|
meson_i2c_set_mask(i2c, REG_CTRL,
|
|
REG_CTRL_START, 0);
|
|
pr_debug("meson i2c: timeout\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
udelay(1);
|
|
cnt++;
|
|
}
|
|
meson_i2c_reset_tokens(i2c);
|
|
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
|
|
|
|
if (readl(i2c->regs + REG_CTRL) & REG_CTRL_ERROR) {
|
|
pr_debug("meson i2c: error\n");
|
|
return -EREMOTEIO;
|
|
}
|
|
|
|
if ((msg->flags & I2C_M_RD) && i2c->count) {
|
|
meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos,
|
|
i2c->count);
|
|
}
|
|
i2c->pos += i2c->count;
|
|
} while (i2c->pos < msg->len);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg,
|
|
int last)
|
|
{
|
|
unsigned long time_left, flags;
|
|
int ret = 0;
|
|
|
|
i2c->msg = msg;
|
|
i2c->last = last;
|
|
i2c->pos = 0;
|
|
i2c->count = 0;
|
|
i2c->error = 0;
|
|
|
|
meson_i2c_reset_tokens(i2c);
|
|
|
|
flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0;
|
|
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags);
|
|
|
|
if (!(msg->flags & I2C_M_NOSTART))
|
|
meson_i2c_do_start(i2c, msg);
|
|
|
|
i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
|
|
meson_i2c_prepare_xfer(i2c);
|
|
reinit_completion(&i2c->done);
|
|
|
|
/* Start the transfer */
|
|
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
|
|
|
|
time_left = msecs_to_jiffies(I2C_TIMEOUT_MS);
|
|
time_left = wait_for_completion_timeout(&i2c->done, time_left);
|
|
|
|
/*
|
|
* Protect access to i2c struct and registers from interrupt
|
|
* handlers triggered by a transfer terminated after the
|
|
* timeout period
|
|
*/
|
|
spin_lock_irqsave(&i2c->lock, flags);
|
|
|
|
/* Abort any active operation */
|
|
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
|
|
|
|
if (!time_left) {
|
|
i2c->state = STATE_IDLE;
|
|
ret = -ETIMEDOUT;
|
|
}
|
|
|
|
if (i2c->error)
|
|
ret = i2c->error;
|
|
|
|
spin_unlock_irqrestore(&i2c->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
|
|
int num)
|
|
{
|
|
struct meson_i2c *i2c = adap->algo_data;
|
|
int i, ret = 0;
|
|
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
ret = pm_runtime_get_sync(i2c->dev);
|
|
if (ret < 0)
|
|
goto out;
|
|
#else
|
|
clk_enable(i2c->clk);
|
|
#endif
|
|
if ((readl(i2c->regs + REG_CTRL) & REG_SCL_LEVEL) == 0 &&
|
|
(readl(i2c->regs + REG_CTRL) & REG_SDA_LEVEL) == 0) {
|
|
/*
|
|
* I2C bus is error
|
|
*/
|
|
dev_dbg(i2c->dev, "I2C BUS is Error, No pull up register\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
/*Abort any active operation, avoid M3 uses this BUS*/
|
|
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
|
|
if (i2c->mode == I2C_POLLING_MODE) {
|
|
for (i = 0; i < num; i++) {
|
|
ret = meson_i2c_xfer_polling_msg(i2c, msgs + i,
|
|
i == num - 1);
|
|
if (ret)
|
|
break;
|
|
}
|
|
} else {
|
|
for (i = 0; i < num; i++) {
|
|
ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1);
|
|
if (ret)
|
|
break;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
out:
|
|
pm_runtime_mark_last_busy(i2c->dev);
|
|
pm_runtime_put_autosuspend(i2c->dev);
|
|
#else
|
|
clk_disable(i2c->clk);
|
|
#endif
|
|
|
|
return ret ?: i;
|
|
}
|
|
|
|
static u32 meson_i2c_func(struct i2c_adapter *adap)
|
|
{
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
}
|
|
|
|
static const struct i2c_algorithm meson_i2c_algorithm = {
|
|
.master_xfer = meson_i2c_xfer,
|
|
.functionality = meson_i2c_func,
|
|
};
|
|
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
static ssize_t speed_show(struct device *child,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
struct meson_i2c *i2c =
|
|
(struct meson_i2c *)dev_get_drvdata(child);
|
|
return sprintf(buf, "%d\n", i2c->frequency);
|
|
}
|
|
|
|
static ssize_t speed_store(struct device *child,
|
|
struct device_attribute *attr,
|
|
const char *buf, size_t size)
|
|
{
|
|
struct meson_i2c *i2c =
|
|
(struct meson_i2c *)dev_get_drvdata(child);
|
|
int ret, val;
|
|
|
|
ret = kstrtouint(buf, 0, &val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
i2c->frequency = val;
|
|
meson_i2c_set_clk_div(i2c);
|
|
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR_RW(speed);
|
|
|
|
int meson_i2c_speed_debug(struct device *dev)
|
|
{
|
|
return sysfs_create_file(&dev->kobj, &dev_attr_speed.attr);
|
|
}
|
|
#endif
|
|
|
|
static int meson_i2c_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct meson_i2c *i2c;
|
|
struct resource *mem;
|
|
struct i2c_timings timings;
|
|
int irq, ret = 0;
|
|
|
|
i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL);
|
|
if (!i2c)
|
|
return -ENOMEM;
|
|
|
|
i2c_parse_fw_timings(&pdev->dev, &timings, true);
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
i2c->frequency = timings.bus_freq_hz;
|
|
|
|
if (fwnode_property_present(&np->fwnode, "retain-fast-mode"))
|
|
i2c->retain_fastmode = 1;
|
|
if (of_property_read_u32(pdev->dev.of_node, "working_mode",
|
|
&i2c->mode))
|
|
i2c->mode = I2C_IRQ_MODE;
|
|
i2c->data = (struct meson_i2c_data *)of_device_get_match_data(&pdev->dev);
|
|
#endif
|
|
i2c->dev = &pdev->dev;
|
|
platform_set_drvdata(pdev, i2c);
|
|
|
|
spin_lock_init(&i2c->lock);
|
|
init_completion(&i2c->done);
|
|
|
|
i2c->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(i2c->clk)) {
|
|
dev_err(&pdev->dev, "can't get device clock\n");
|
|
return PTR_ERR(i2c->clk);
|
|
}
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
|
|
if (IS_ERR(i2c->regs))
|
|
return PTR_ERR(i2c->regs);
|
|
if (i2c->data->tee) {
|
|
/* get i2c tee_id property */
|
|
ret = of_property_read_u32(pdev->dev.of_node, "tee_id",
|
|
&i2c->data->tee_id);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "not config tee_id\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "can't find IRQ\n");
|
|
return irq;
|
|
}
|
|
if (i2c->mode == I2C_IRQ_MODE) {
|
|
ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "can't request IRQ\n");
|
|
return ret;
|
|
}
|
|
}
|
|
#ifndef CONFIG_AMLOGIC_MODIFY
|
|
ret = clk_prepare(i2c->clk);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "can't prepare clock\n");
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
strscpy(i2c->adap.name, "Meson I2C adapter",
|
|
sizeof(i2c->adap.name));
|
|
i2c->adap.owner = THIS_MODULE;
|
|
i2c->adap.algo = &meson_i2c_algorithm;
|
|
i2c->adap.dev.parent = &pdev->dev;
|
|
i2c->adap.dev.of_node = np;
|
|
i2c->adap.algo_data = i2c;
|
|
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
i2c->irq = irq;
|
|
/* Disable the interrupt so that the system can enter low-power mode */
|
|
if (i2c->mode == I2C_IRQ_MODE)
|
|
disable_irq(i2c->irq);
|
|
pm_runtime_enable(i2c->dev);
|
|
pm_runtime_set_autosuspend_delay(i2c->dev, MESON_I2C_PM_TIMEOUT);
|
|
pm_runtime_use_autosuspend(i2c->dev);
|
|
|
|
ret = pm_runtime_get_sync(i2c->dev);
|
|
if (ret < 0) {
|
|
pm_runtime_put_noidle(i2c->dev);
|
|
pm_runtime_disable(i2c->dev);
|
|
return ret;
|
|
}
|
|
|
|
/* speed sysfs */
|
|
ret = meson_i2c_speed_debug(&pdev->dev);
|
|
if (ret)
|
|
dev_err(&pdev->dev, "Creat i2c speed debug sysfs failed\n");
|
|
i2c->clk_rate = clk_get_rate(i2c->clk);
|
|
if (i2c->clk_rate == 0) {
|
|
dev_err(&pdev->dev, "failed to get clk rate\n");
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
/*
|
|
* A transfer is triggered when START bit changes from 0 to 1.
|
|
* Ensure that the bit is set to 0 after probe
|
|
*/
|
|
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
meson_i2c_set_clk_div(i2c);
|
|
pm_runtime_mark_last_busy(i2c->dev);
|
|
pm_runtime_put_autosuspend(i2c->dev);
|
|
#else
|
|
meson_i2c_set_clk_div(i2c, timings.bus_freq_hz);
|
|
#endif
|
|
ret = i2c_add_adapter(&i2c->adap);
|
|
if (ret < 0) {
|
|
#ifndef CONFIG_AMLOGIC_MODIFY
|
|
clk_unprepare(i2c->clk);
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
static void meson_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct meson_i2c *i2c = platform_get_drvdata(pdev);
|
|
int ret;
|
|
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
|
if (ret < 0)
|
|
return;
|
|
|
|
i2c_del_adapter(&i2c->adap);
|
|
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
}
|
|
#else
|
|
static void meson_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct meson_i2c *i2c = platform_get_drvdata(pdev);
|
|
|
|
i2c_del_adapter(&i2c->adap);
|
|
clk_unprepare(i2c->clk);
|
|
}
|
|
#endif
|
|
|
|
static int meson_i2c_put(struct meson_i2c *i2c)
|
|
{
|
|
if (i2c->mode == I2C_IRQ_MODE)
|
|
disable_irq(i2c->irq);
|
|
pinctrl_pm_select_sleep_state(i2c->dev);
|
|
clk_disable_unprepare(i2c->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int meson_i2c_regain(struct meson_i2c *i2c)
|
|
{
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(i2c->clk);
|
|
if (ret < 0) {
|
|
dev_err(i2c->dev, "can not enable clock\n");
|
|
return ret;
|
|
}
|
|
pinctrl_pm_select_default_state(i2c->dev);
|
|
if (i2c->mode == I2C_IRQ_MODE)
|
|
enable_irq(i2c->irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_HIBERNATION
|
|
static int meson_i2c_freeze(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct meson_i2c *i2c = (struct meson_i2c *)dev_get_drvdata(dev);
|
|
|
|
if (i2c->is_runtime_sleep)
|
|
return 0;
|
|
ret = meson_i2c_put(i2c);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int meson_i2c_thaw(struct device *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int meson_i2c_restore(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct meson_i2c *i2c = (struct meson_i2c *)dev_get_drvdata(dev);
|
|
|
|
if (i2c->is_runtime_sleep)
|
|
return 0;
|
|
ret = meson_i2c_regain(i2c);
|
|
meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
|
|
meson_i2c_set_clk_div(i2c);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
static int __maybe_unused meson_i2c_runtime_suspend(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct meson_i2c *i2c = (struct meson_i2c *)dev_get_drvdata(dev);
|
|
|
|
ret = meson_i2c_put(i2c);
|
|
i2c->is_runtime_sleep = true;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __maybe_unused meson_i2c_runtime_resume(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct meson_i2c *i2c = (struct meson_i2c *)dev_get_drvdata(dev);
|
|
|
|
ret = meson_i2c_regain(i2c);
|
|
i2c->is_runtime_sleep = false;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dev_pm_ops meson_i2c_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(meson_i2c_runtime_suspend,
|
|
meson_i2c_runtime_resume, NULL)
|
|
#ifdef CONFIG_HIBERNATION
|
|
.freeze = meson_i2c_freeze,
|
|
.thaw = meson_i2c_thaw,
|
|
.restore = meson_i2c_restore,
|
|
#endif
|
|
};
|
|
#endif
|
|
|
|
static struct meson_i2c_data i2c_tee_data = {
|
|
.tee = true,
|
|
};
|
|
|
|
static struct meson_i2c_data i2c_normal_data = {
|
|
.tee = false,
|
|
};
|
|
|
|
static const struct of_device_id meson_i2c_match[] = {
|
|
{ .compatible = "amlogic,meson-i2c",
|
|
.data = &i2c_normal_data
|
|
},
|
|
{
|
|
.compatible = "amlogic,meson-tee-i2c",
|
|
.data = &i2c_tee_data
|
|
},
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, meson_i2c_match);
|
|
|
|
static struct platform_driver meson_i2c_driver = {
|
|
.probe = meson_i2c_probe,
|
|
.remove = meson_i2c_remove,
|
|
.driver = {
|
|
.name = "meson-i2c",
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
.pm = &meson_i2c_pm_ops,
|
|
#endif
|
|
.of_match_table = meson_i2c_match,
|
|
},
|
|
};
|
|
|
|
int __init i2c_meson_init(void)
|
|
{
|
|
return platform_driver_register(&meson_i2c_driver);
|
|
}
|
|
|
|
void __exit i2c_meson_exit(void)
|
|
{
|
|
platform_driver_unregister(&meson_i2c_driver);
|
|
}
|
|
|
|
MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver");
|
|
MODULE_AUTHOR("Beniamino Galvani <[email protected]>");
|
|
MODULE_LICENSE("GPL v2");
|