1000 lines
24 KiB
C
1000 lines
24 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_domain.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/arm-smccc.h>
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// #include <linux/amlogic/secure_pwm_i2c.h>
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#include <dt-bindings/i2c/i2c-meson.h>
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#include <linux/delay.h>
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// #define I2C_DEBUG
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// #define I2C_PXP
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#define I2C_PM_RUNTIME
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#define FUTURE_USE 0
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/* Meson I2C register map */
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#define REG_CFG_RDY 0x00
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#define REG_CFG_I2C 0x04
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#define REG_CFG_START 0x08
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#define REG_CFG_BUS 0x0c
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#define REG_TX_RD_ADDR 0x10
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#define REG_TX_WR_ADDR 0x14
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#define REG_RX_RD_ADDR 0x18
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#define REG_RX_WR_ADDR 0x1c
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#define REG_CGF_TX 0x20
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#define REG_CGF_RX 0x24
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#define REG_CGF_IRQ_STATE 0x30
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#define REG_CGF_IRQ_ENABLE 0x34
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#define REG_SHAKE_BLK_CNT 0x38 //could check numbers of bytes send
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/* CFG RDY fields */
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#define RDY_TEE_ONLY BIT(1)
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#define RDY_IF BIT(0)
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/* CFG I2C fields */
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#define I2C_RX_THR GENMASK(23, 16)
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#define I2C_TX_THR GENMASK(15, 8)
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#define I2C_DMA BIT(4)
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#define I2C_HW_NEG BIT(3)
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#define I2C_HW_POS BIT(2)
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#define I2C_JOIN_RX BIT(1)
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#define I2C_JOIN_TX BIT(0)
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#define I2C_TX_THR_DIV 2
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/* CFG BUS fields */
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#define BUS_NO_STOP BIT(18)//after soc c5 support this bit. others invalid.
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#define BUS_SPEED_MODE BIT(17)
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#define BUS_SLAVE_MODE BIT(16)
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#define BUS_FILTER_MASK GENMASK(15, 12)
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/*SCL = clk/b_ratio if b_ratio<=8, SCL = clk/8 */
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#define BUS_RATIO_MASK GENMASK(11, 0)
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/* CFG START fields */
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#define START_STRAT BIT(31)
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#define START_LEN GENMASK(23, 12)
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#define START_LEN_SHIFT 12
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#define START_10_BITS BIT(11) /*only 7bit now*/
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#define START_SLAVE_ADDR GENMASK(10, 1)
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#define START_READ BIT(0)
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/* CFG TX_RX fields */
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#define TX_RX_EMPTY BIT(9)
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#define TX_RX_FULL BIT(8)
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#define TX_RX_DATA GENMASK(7, 0)
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/* SHAKE_BLK_CNT fields */
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#define BLK_CNT_MASK GENMASK(16, 4)
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#define BLK_CNT_SHIFTS 4
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/*CGF IRQ fields */
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#define RCH_ERROR BIT(0)
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#define WCH_ERROR BIT(1)
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#define NCK_ERROR BIT(2)
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#define RX_EMPTY BIT(3)
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#define TX_FULL BIT(4)
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#define RX_FIFO_READ BIT(5)
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#define TX_FIFO_WRITE BIT(6)
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#define PHY_DONE BIT(7)
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#define TRANS_ERROR (RCH_ERROR | WCH_ERROR | NCK_ERROR)
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#define TRANS_DONE (PHY_DONE | TRANS_ERROR)
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/* enable irq, critical trans done bit must be set.
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* tx/rx thresh bit used for continuously transfer,
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* set it manul when transfer.
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* TX_FULL RX_EMPTY not used.
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* NACK ERROR can not be use in gxlx4, it will cause down signal at scl after nack.
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*/
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#define ENABLE_IRQ_BIT (NCK_ERROR | RCH_ERROR | WCH_ERROR | PHY_DONE)
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//| RX_FIFO_READ | TX_FIFO_WRITE)
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/*A9 and new IRQ fields*/
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#define A9_NCK_ERROR BIT(0)
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#define A9_RX_EMPTY BIT(1)
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#define A9_RX_FULL BIT(2)
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#define A9_TX_EMPTY BIT(3)
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#define A9_TX_FULL BIT(4)
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//#define A9_RX_FIFO_READ BIT(5) same as the old
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//#define A9_TX_FIFO_WRITE BIT(6) same as the old
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//#define A9_PHY_DONE BIT(7) same as the old
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#define A9_TASK_DONE BIT(8)
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#define A9_ALL_DONE BIT(9)
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#define A9_TRANS_DONE (PHY_DONE | A9_NCK_ERROR)
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#define A9_TRANS_ERROR (A9_NCK_ERROR)
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#define A9_ENABLE_IRQ_BIT (A9_NCK_ERROR | PHY_DONE)
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//if use thresh mode, should be set at start.
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#define THRESH_MODE (RX_FIFO_READ | TX_FIFO_WRITE)
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#define REG_FIFO_BASE 0x80
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/* keep the same with I2C_TIMEOUT_MS */
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#define MESON_I2C_PM_TIMEOUT 500
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#define I2C_TIMEOUT_MS 500
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#define MESON_I2C_PM_TIMEOUT 500
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enum {
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STATE_IDLE,
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STATE_READ,
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STATE_WRITE,
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STATE_WAIT,
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};
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struct meson_i2c_data {
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bool tee;
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u32 tee_id;
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u32 enable_irq_bits;
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u32 xfer_done_bits;
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u32 xfer_err_bits;
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};
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/**
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* struct meson_i2c - Meson I2C device private data
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*
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* @adap: I2C adapter instance
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* @dev: Pointer to device structure
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* @regs: Base address of the device memory mapped registers
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* @clk: Pointer to clock structure
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* @msg: Pointer to the current I2C message
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* @state: Current state in the driver state machine
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* @count: Number of bytes to be sent/received in current transfer
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* @last: The last msg flag
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* @pos: Current position in the send/receive buffer
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* @error: Flag set when an error is received
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* @lock: To avoid race conditions between irq handler and xfer code
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* @done: Completion used to wait for transfer termination
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* @frequency: Operating frequency of I2C bus clock
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* @data: Pointer to the controller's platform data
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*@mode: I2C's transfer mode irq or polling
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*/
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struct meson_i2c {
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struct i2c_adapter adap;
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struct device *dev;
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void __iomem *regs;
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struct clk *clk;
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struct i2c_msg *msg;
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int state;
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int count;
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int pos;
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bool last;
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int error;
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int fifo_depth;
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spinlock_t lock; //protection for i2c controller critical section
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struct completion done;
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#ifdef CONFIG_AMLOGIC_MODIFY
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unsigned long clk_rate;
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unsigned int frequency;
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int retain_fastmode;
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int irq;
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bool is_runtime_sleep;
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#endif
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struct meson_i2c_data *data;
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int mode;
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};
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static void meson_i2c_writel(struct meson_i2c *i2c, u32 data, int reg)
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{
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#if FUTURE_USE
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struct arm_smccc_res res;
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if (i2c->data->tee)
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arm_smccc_smc(SECURE_PWM_I2C, SECID_I2C, i2c->data->tee_id,
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reg, data, 0, 0, 0, &res);
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else
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#endif
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writel(data, i2c->regs + reg);
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}
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static inline void meson_i2c_dump_reg(struct meson_i2c *i2c, const char *func, int line)
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{
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#ifdef I2C_DEBUG
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u32 data;
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int i;
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trace_printk("%s %s, line:%d\n", dev_name(i2c->dev), func, line);
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for (i = 0 ; i < 8; i++) {
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data = readl(i2c->regs + i * 4);
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trace_printk("%s i2c reg%x : 0x%x\n", dev_name(i2c->dev), i, data);
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}
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for (i = 0xb ; i < 0xf; i++) {
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data = readl(i2c->regs + i * 4);
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trace_printk("%s i2c reg%x : 0x%x\n", dev_name(i2c->dev), i, data);
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}
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#endif
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}
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static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
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u32 val)
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{
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u32 data;
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data = readl(i2c->regs + reg);
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data &= ~mask;
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data |= val & mask;
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meson_i2c_writel(i2c, data, reg);
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}
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/*
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* SCL = clk/b_ratio. if b_ratio<=8, SCL = clk/8
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*/
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static void meson_i2c_set_clk_div(struct meson_i2c *i2c)
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{
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unsigned long clk_rate = i2c->clk_rate;
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unsigned int div;
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div = DIV_ROUND_UP(clk_rate, i2c->frequency);
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/* clock divider has 12 bits */
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if (div >= (1 << 12))
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dev_err(i2c->dev, "requested bus frequency too low\n");
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else if (div <= 8)
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dev_err(i2c->dev, "requested bus frequency too high\n");
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#ifdef I2C_PXP
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div = 0x40;
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#endif
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/* CFG_BUS reg:11 - 0 bits
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* BUS_SPEED_MODE for HW timming
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*/
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meson_i2c_set_mask(i2c, REG_CFG_BUS,
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BUS_RATIO_MASK | BUS_SPEED_MODE, div | BUS_SPEED_MODE);
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#ifdef I2C_DEBUG
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trace_printk("%s %s: clk %lu, freq %u, div %u\n",
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dev_name(i2c->dev), __func__,
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clk_rate, i2c->frequency, div);
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#endif
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}
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static void reset_fifo_pos(struct meson_i2c *i2c)
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{
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meson_i2c_writel(i2c, 0x00, REG_TX_RD_ADDR);
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meson_i2c_writel(i2c, 0x00, REG_TX_WR_ADDR);
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/* Must reset rx_wr_addr before rx_rd_addr for continues read.
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* Because reset rd will pull data to fifo, so we need reset wr early.
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* And then, data will be push rightly to 1st fifo position.
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*/
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meson_i2c_writel(i2c, 0x00, REG_RX_WR_ADDR);
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meson_i2c_writel(i2c, 0x00, REG_RX_RD_ADDR);
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}
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static int controller_is_error(struct meson_i2c *i2c)
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{
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int ret = 0;
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if (readl(i2c->regs + REG_CGF_IRQ_STATE) & i2c->data->xfer_err_bits) {
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#ifdef I2C_DEBUG
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trace_printk("%s i2c controller error: 0x%x\n", dev_name(i2c->dev),
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readl(i2c->regs + REG_CGF_IRQ_STATE));
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#endif
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ret = -ENXIO;
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}
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return ret;
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}
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static int controller_is_done(struct meson_i2c *i2c)
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{
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return readl(i2c->regs + REG_CGF_IRQ_STATE) & i2c->data->xfer_done_bits;
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}
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static void clear_irq_status(struct meson_i2c *i2c, u32 irq_bits)
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{
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meson_i2c_writel(i2c, irq_bits, REG_CGF_IRQ_STATE);
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}
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static int wait_controller_done(struct meson_i2c *i2c)
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{
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u32 time_cnt = 0;
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int ret = 0;
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while (!controller_is_done(i2c)) {
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if (time_cnt > I2C_TIMEOUT_MS * 1000)
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return -ETIMEDOUT;
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udelay(1);
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time_cnt++;
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}
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ret = controller_is_error(i2c);
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return ret;
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}
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static int get_tx_count(struct meson_i2c *i2c)
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{
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int rd_val;
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rd_val = (readl(i2c->regs + REG_SHAKE_BLK_CNT) & BLK_CNT_MASK) >> BLK_CNT_SHIFTS;
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return rd_val;
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}
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static int wait_tx_done(struct meson_i2c *i2c, u32 des_count)
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{
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u32 time_cnt = 0;
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int ret = 0;
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while (get_tx_count(i2c) != des_count) {
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if (time_cnt > I2C_TIMEOUT_MS * 1000)
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return -ETIMEDOUT;
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udelay(1);
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time_cnt++;
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ret = controller_is_error(i2c);
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if (ret)
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return ret;
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}
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return ret;
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}
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static void meson_i2c_init(struct meson_i2c *i2c)
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{
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meson_i2c_set_mask(i2c, REG_CFG_BUS, BUS_FILTER_MASK, 1 << 12);
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clear_irq_status(i2c, 0xffff);//clear all irq
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meson_i2c_writel(i2c, i2c->data->enable_irq_bits, REG_CGF_IRQ_ENABLE);
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meson_i2c_set_mask(i2c, REG_CFG_BUS, BUS_FILTER_MASK | BUS_NO_STOP, 1 << 12 | BUS_NO_STOP);
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/* set rx thresh, when fifo has data and fifo full will generate irq for cpu read.
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* set tx thresh, when fifo empty will generate irq for continue transfer.
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* set fifo depth and should clear dma mode avoid tcon driver set DMA,
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* because TCON driver will OP i2c DMA in there driver.
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*/
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i2c->fifo_depth = 16;
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meson_i2c_set_mask(i2c, REG_CFG_I2C, I2C_DMA | I2C_RX_THR | I2C_TX_THR,
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i2c->fifo_depth << 16 | (i2c->fifo_depth / I2C_TX_THR_DIV) << 8);
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reset_fifo_pos(i2c);
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meson_i2c_set_clk_div(i2c);
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}
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static void meson_i2c_add_stop(struct meson_i2c *i2c)
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{
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meson_i2c_set_mask(i2c, REG_CFG_BUS, BUS_NO_STOP, 0);
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}
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static void meson_i2c_push_data_to_user(struct meson_i2c *i2c, u8 data)
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{
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u8 *buf = i2c->msg->buf + i2c->pos;
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i2c->count = 1;
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*buf = data;
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#ifdef I2C_DEBUG
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trace_printk("%s %s: data %08x\n", dev_name(i2c->dev), __func__, *buf);
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#endif
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}
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static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len)
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{
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if (!i2c->msg->len) {//this i2c module when trans 0 byte, must put at least 1.
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meson_i2c_writel(i2c, 0x00, REG_CGF_TX);
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return;
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}
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for (int i = 0; i < len; i++, buf++) {
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meson_i2c_writel(i2c, *buf, REG_CGF_TX);
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#ifdef I2C_DEBUG
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trace_printk("%s %s: data %08x\n", dev_name(i2c->dev), __func__, *buf);
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#endif
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}
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}
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static void meson_i2c_prepare_xfer(struct meson_i2c *i2c, bool full_fill)
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{
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bool write = !(i2c->msg->flags & I2C_M_RD);
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if (write) {
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if (i2c->mode == I2C_POLLING_MODE || full_fill)
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i2c->count = min(i2c->msg->len - i2c->pos, i2c->fifo_depth);
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else
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i2c->count = min(i2c->msg->len - i2c->pos,
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i2c->fifo_depth / I2C_TX_THR_DIV);
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meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
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}
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}
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/* three case should be check in irq:
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* 1.trans done
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* 2.RX thresh(fifo full) ------> pull data
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* 3.TX thresh(fifo empty) ------>push data to fifo
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*
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*/
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static irqreturn_t meson_i2c_irq(int irqno, void *dev_id)
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{
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struct meson_i2c *i2c = dev_id;
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int ret;
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u32 rd_len, i;
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u32 rd_val;
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spin_lock(&i2c->lock);
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ret = controller_is_error(i2c);
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if (ret) {
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#ifdef I2C_DEBUG
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trace_printk("%s IRQ controller error\n", dev_name(i2c->dev));
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#endif
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i2c->error = ret;
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goto complete_irq_out;
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}
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switch (i2c->state) {
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case STATE_READ:
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meson_i2c_dump_reg(i2c, __func__, __LINE__);
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rd_len = min(i2c->msg->len - i2c->pos, i2c->fifo_depth);
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#ifdef I2C_DEBUG
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trace_printk("%s thresh for rx rd-len:%d\n", dev_name(i2c->dev), rd_len);
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#endif
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for (i = 0; i < rd_len; i++) {
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rd_val = readl(i2c->regs + REG_CGF_RX);
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#ifdef I2C_DEBUG
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trace_printk("%s thresh for rx RX reg value:0x%x\n",
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dev_name(i2c->dev), rd_val);
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#endif
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meson_i2c_push_data_to_user(i2c, rd_val & TX_RX_DATA);
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i2c->pos += i2c->count;
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}
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clear_irq_status(i2c, RX_FIFO_READ);//rx must clear thresh after read fifo
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break;
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case STATE_WRITE:
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#ifdef I2C_DEBUG
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trace_printk("%s thresh for tx\n", dev_name(i2c->dev));
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#endif
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meson_i2c_dump_reg(i2c, __func__, __LINE__);
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meson_i2c_prepare_xfer(i2c, false);
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if ((i2c->pos + i2c->fifo_depth / I2C_TX_THR_DIV) >= i2c->msg->len)
|
|
meson_i2c_set_mask(i2c, REG_CGF_IRQ_ENABLE, TX_FIFO_WRITE, 0);
|
|
clear_irq_status(i2c, TX_FIFO_WRITE);//tx must clear thresh after write fifo
|
|
i2c->pos += i2c->count;
|
|
break;
|
|
case STATE_IDLE:
|
|
dev_warn(i2c->dev, "i2c irq triggered abnormally!!!, irq_state:0x%x,irq_en:0x%x\n",
|
|
readl(i2c->regs + REG_CGF_IRQ_STATE),
|
|
readl(i2c->regs + REG_CGF_IRQ_ENABLE));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
//check controller done?
|
|
if (!controller_is_done(i2c)) {
|
|
goto irq_trans_out;
|
|
} else {
|
|
#ifdef I2C_DEBUG
|
|
trace_printk("%s i2c irq controller_is_done\n",
|
|
dev_name(i2c->dev));
|
|
#endif
|
|
if (i2c->state == STATE_READ && (i2c->msg->len - i2c->pos)) {//read not complete
|
|
#ifdef I2C_DEBUG
|
|
trace_printk("%s i2c irq done but read not complete\n",
|
|
dev_name(i2c->dev));
|
|
#endif
|
|
goto irq_trans_out;
|
|
}
|
|
}
|
|
|
|
complete_irq_out:
|
|
reset_fifo_pos(i2c);
|
|
complete(&i2c->done);
|
|
i2c->state = STATE_IDLE;
|
|
meson_i2c_set_mask(i2c, REG_CGF_IRQ_ENABLE,
|
|
RX_FIFO_READ | TX_FIFO_WRITE, 0);//disable TX/RX irq bits
|
|
clear_irq_status(i2c, 0xffff);//clear all irq
|
|
irq_trans_out:
|
|
#ifdef I2C_DEBUG
|
|
trace_printk("%s IRQ out\n", dev_name(i2c->dev));
|
|
#endif
|
|
meson_i2c_dump_reg(i2c, __func__, __LINE__);
|
|
spin_unlock(&i2c->lock);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
|
|
{
|
|
unsigned int reg_val;
|
|
unsigned int trans_len;
|
|
|
|
trans_len = msg->len;
|
|
if (i2c->mode == I2C_POLLING_MODE) {
|
|
//if TX and not last xfer, need add no stop
|
|
if (!(msg->flags & I2C_M_RD) && !i2c->last && msg->len)
|
|
trans_len = msg->len + 1;
|
|
}
|
|
reg_val = (msg->addr << 1) |
|
|
((msg->flags & I2C_M_RD) ? START_READ : 0) |
|
|
((trans_len) << 12) | START_STRAT;
|
|
meson_i2c_set_mask(i2c, REG_CFG_START,
|
|
START_STRAT | START_SLAVE_ADDR | START_READ | START_LEN, reg_val);
|
|
//NACK irq will be clear validly only after start signal
|
|
clear_irq_status(i2c, 0xffff);//clear all irq
|
|
if (trans_len > i2c->fifo_depth) {
|
|
reg_val = (msg->flags & I2C_M_RD) ? RX_FIFO_READ : TX_FIFO_WRITE;
|
|
meson_i2c_set_mask(i2c, REG_CGF_IRQ_ENABLE,
|
|
RX_FIFO_READ | TX_FIFO_WRITE, reg_val);//enable thresh mode
|
|
}
|
|
meson_i2c_dump_reg(i2c, __func__, __LINE__);
|
|
}
|
|
|
|
static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg, bool last)
|
|
{
|
|
unsigned long time_left, flags;
|
|
int ret = 0;
|
|
|
|
i2c->msg = msg;
|
|
i2c->pos = 0;
|
|
i2c->count = 0;
|
|
i2c->error = 0;
|
|
|
|
i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
|
|
meson_i2c_prepare_xfer(i2c, true);
|
|
i2c->pos += i2c->count;//every prepare data pushed, should increase pos.
|
|
reinit_completion(&i2c->done);
|
|
|
|
if (last)
|
|
meson_i2c_add_stop(i2c);
|
|
/* Start the transfer */
|
|
meson_i2c_do_start(i2c, msg);
|
|
|
|
time_left = msecs_to_jiffies(I2C_TIMEOUT_MS);
|
|
time_left = wait_for_completion_timeout(&i2c->done, time_left);
|
|
|
|
/*
|
|
* Protect access to i2c struct and registers from interrupt
|
|
* handlers triggered by a transfer terminated after the
|
|
* timeout period
|
|
*/
|
|
spin_lock_irqsave(&i2c->lock, flags);
|
|
|
|
if (!time_left) {
|
|
/*to do. maybe reset i2c for stop*/
|
|
i2c->state = STATE_IDLE;
|
|
ret = -ETIMEDOUT;
|
|
}
|
|
|
|
if (i2c->error)
|
|
ret = i2c->error;
|
|
|
|
spin_unlock_irqrestore(&i2c->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int meson_i2c_no_stop(struct meson_i2c *i2c)
|
|
{
|
|
int ret = 0;
|
|
int trans_cnt;
|
|
u32 time_cnt = 0;
|
|
|
|
//check data trans done
|
|
while (true) {
|
|
trans_cnt = (readl(i2c->regs + REG_SHAKE_BLK_CNT) & BLK_CNT_MASK) >> BLK_CNT_SHIFTS;
|
|
if (trans_cnt >= i2c->msg->len)
|
|
break;
|
|
/*time out*/
|
|
if (time_cnt > I2C_TIMEOUT_MS * 1000) {
|
|
ret = -ETIMEDOUT;
|
|
goto no_stop_out;
|
|
}
|
|
udelay(1);
|
|
time_cnt++;
|
|
}
|
|
udelay(20);//must delay controller idle
|
|
pinctrl_pm_select_sleep_state(i2c->dev);//release SDA/SCL line
|
|
meson_i2c_writel(i2c, i2c->msg->len << START_LEN_SHIFT, REG_CFG_START);//stop controller
|
|
meson_i2c_writel(i2c, 0xaf, REG_CGF_TX);//write visual xfer
|
|
//wait trans done
|
|
ret = wait_controller_done(i2c);
|
|
|
|
no_stop_out:
|
|
reset_fifo_pos(i2c);
|
|
pinctrl_pm_select_default_state(i2c->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int meson_i2c_xfer_polling_msg(struct meson_i2c *i2c, struct i2c_msg *msg, bool last)
|
|
{
|
|
int rd_val, time_cnt, ret = 0;
|
|
|
|
i2c->msg = msg;
|
|
i2c->pos = 0;
|
|
i2c->count = 0;
|
|
i2c->last = last;
|
|
meson_i2c_do_start(i2c, msg);
|
|
do {
|
|
if (msg->flags & I2C_M_RD) {//for rx
|
|
time_cnt = 0;
|
|
do {
|
|
rd_val = readl(i2c->regs + REG_CGF_RX);
|
|
if (time_cnt > I2C_TIMEOUT_MS * 1000) {
|
|
ret = -ETIMEDOUT;
|
|
goto xfer_out;
|
|
}
|
|
udelay(1);
|
|
time_cnt++;
|
|
ret = controller_is_error(i2c);
|
|
if (ret)
|
|
goto xfer_out;
|
|
} while (rd_val & TX_RX_EMPTY);//waiting data
|
|
meson_i2c_push_data_to_user(i2c, rd_val & TX_RX_DATA);
|
|
} else { //for tx
|
|
meson_i2c_prepare_xfer(i2c, true);
|
|
ret = wait_tx_done(i2c, i2c->pos + i2c->count);
|
|
if (ret)
|
|
goto xfer_out;
|
|
}
|
|
i2c->pos += i2c->count;
|
|
} while (i2c->pos < msg->len);
|
|
|
|
//if TX and not last xfer, need add no stop
|
|
if (!(msg->flags & I2C_M_RD) && !i2c->last && msg->len) {
|
|
ret = meson_i2c_no_stop(i2c);
|
|
if (ret)
|
|
goto xfer_out;
|
|
} else {
|
|
//wait trans done
|
|
ret = wait_controller_done(i2c);
|
|
if (ret)
|
|
goto xfer_out;
|
|
}
|
|
|
|
xfer_out:
|
|
clear_irq_status(i2c, 0xffff);//clear all irq
|
|
reset_fifo_pos(i2c);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
|
|
int num)
|
|
{
|
|
struct meson_i2c *i2c = adap->algo_data;
|
|
int i, ret = 0;
|
|
|
|
#ifdef I2C_PM_RUNTIME
|
|
ret = pm_runtime_get_sync(i2c->dev);
|
|
if (ret < 0)
|
|
goto out;
|
|
#endif
|
|
meson_i2c_init(i2c);//must init i2c in every xfer
|
|
for (i = 0; i < num; i++) {
|
|
if (i2c->mode == I2C_POLLING_MODE)
|
|
ret = meson_i2c_xfer_polling_msg(i2c, msgs + i, i == num - 1);
|
|
else
|
|
ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1);
|
|
if (ret)
|
|
break;
|
|
}
|
|
|
|
#ifdef I2C_PM_RUNTIME
|
|
out:
|
|
pm_runtime_mark_last_busy(i2c->dev);
|
|
pm_runtime_put_autosuspend(i2c->dev);
|
|
#endif
|
|
return ret ?: i;
|
|
}
|
|
|
|
static u32 meson_i2c_func(struct i2c_adapter *adap)
|
|
{
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
}
|
|
|
|
static const struct i2c_algorithm meson_i2c_algorithm = {
|
|
.master_xfer = meson_i2c_xfer,
|
|
.functionality = meson_i2c_func,
|
|
};
|
|
|
|
static ssize_t speed_show(struct device *child,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
struct meson_i2c *i2c =
|
|
(struct meson_i2c *)dev_get_drvdata(child);
|
|
return sprintf(buf, "%d\n", i2c->frequency);
|
|
}
|
|
|
|
static ssize_t speed_store(struct device *child,
|
|
struct device_attribute *attr,
|
|
const char *buf, size_t size)
|
|
{
|
|
struct meson_i2c *i2c =
|
|
(struct meson_i2c *)dev_get_drvdata(child);
|
|
int ret, val;
|
|
|
|
ret = kstrtouint(buf, 0, &val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
i2c->frequency = val;
|
|
meson_i2c_set_clk_div(i2c);
|
|
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR_RW(speed);
|
|
|
|
static int meson_i2c_speed_debug(struct device *dev)
|
|
{
|
|
return sysfs_create_file(&dev->kobj, &dev_attr_speed.attr);
|
|
}
|
|
|
|
static int meson_i2c_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct meson_i2c *i2c;
|
|
struct i2c_timings timings;
|
|
int irq, ret;
|
|
|
|
i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL);
|
|
if (!i2c)
|
|
return -ENOMEM;
|
|
|
|
i2c_parse_fw_timings(&pdev->dev, &timings, true);
|
|
i2c->frequency = timings.bus_freq_hz;
|
|
i2c->data = (struct meson_i2c_data *)of_device_get_match_data(&pdev->dev);
|
|
i2c->dev = &pdev->dev;
|
|
platform_set_drvdata(pdev, i2c);
|
|
|
|
spin_lock_init(&i2c->lock);
|
|
init_completion(&i2c->done);
|
|
|
|
i2c->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(i2c->clk)) {
|
|
dev_err(&pdev->dev, "can't get device clock\n");
|
|
return PTR_ERR(i2c->clk);
|
|
}
|
|
i2c->clk_rate = clk_get_rate(i2c->clk);
|
|
if (i2c->clk_rate == 0) {
|
|
dev_err(&pdev->dev, "failed to get clk rate\n");
|
|
return -EINVAL;
|
|
}
|
|
i2c->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(i2c->regs))
|
|
return PTR_ERR(i2c->regs);
|
|
if (i2c->data->tee) {
|
|
/* get i2c tee_id property */
|
|
ret = of_property_read_u32(pdev->dev.of_node, "tee_id",
|
|
&i2c->data->tee_id);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "not config tee_id\n");
|
|
return ret;
|
|
}
|
|
}
|
|
/* init i2c before req irq, avoid it's old states trigger irq.
|
|
* and must init i2c after get clock rate, because it will set speed.
|
|
*/
|
|
meson_i2c_init(i2c);
|
|
if (of_property_read_u32(pdev->dev.of_node, "working_mode",
|
|
&i2c->mode)) {
|
|
i2c->mode = I2C_IRQ_MODE;
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "can't find IRQ\n");
|
|
return irq;
|
|
}
|
|
ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "can't request IRQ\n");
|
|
return ret;
|
|
}
|
|
i2c->irq = irq;
|
|
#ifdef I2C_PM_RUNTIME
|
|
/* Disable the interrupt so that the system can enter low-power mode */
|
|
disable_irq(i2c->irq);
|
|
#endif
|
|
}
|
|
|
|
strscpy(i2c->adap.name, "Meson I2C V2 adapter",
|
|
sizeof(i2c->adap.name));
|
|
i2c->adap.owner = THIS_MODULE;
|
|
i2c->adap.algo = &meson_i2c_algorithm;
|
|
i2c->adap.dev.parent = &pdev->dev;
|
|
i2c->adap.dev.of_node = np;
|
|
i2c->adap.algo_data = i2c;
|
|
#ifdef I2C_PM_RUNTIME
|
|
pm_runtime_enable(i2c->dev);
|
|
pm_runtime_set_autosuspend_delay(i2c->dev, MESON_I2C_PM_TIMEOUT);
|
|
pm_runtime_use_autosuspend(i2c->dev);
|
|
|
|
ret = pm_runtime_get_sync(i2c->dev);
|
|
if (ret < 0) {
|
|
pm_runtime_put_noidle(i2c->dev);
|
|
pm_runtime_disable(i2c->dev);
|
|
return ret;
|
|
}
|
|
#endif
|
|
/* speed sysfs */
|
|
ret = meson_i2c_speed_debug(&pdev->dev);
|
|
if (ret)
|
|
dev_err(&pdev->dev, "Creat i2c speed debug sysfs failed\n");
|
|
#ifdef I2C_PM_RUNTIME
|
|
pm_runtime_mark_last_busy(i2c->dev);
|
|
pm_runtime_put_autosuspend(i2c->dev);
|
|
#endif
|
|
ret = i2c_add_adapter(&i2c->adap);
|
|
if (ret < 0)
|
|
return ret;
|
|
return 0;
|
|
}
|
|
|
|
static void meson_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct meson_i2c *i2c = platform_get_drvdata(pdev);
|
|
#ifdef I2C_PM_RUNTIME
|
|
int ret;
|
|
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
|
if (ret < 0)
|
|
return;
|
|
#endif
|
|
i2c_del_adapter(&i2c->adap);
|
|
#ifdef I2C_PM_RUNTIME
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
#endif
|
|
}
|
|
|
|
static int meson_i2c_put(struct meson_i2c *i2c)
|
|
{
|
|
if (i2c->mode == I2C_IRQ_MODE)
|
|
disable_irq(i2c->irq);
|
|
pinctrl_pm_select_sleep_state(i2c->dev);
|
|
clk_disable_unprepare(i2c->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int meson_i2c_regain(struct meson_i2c *i2c)
|
|
{
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(i2c->clk);
|
|
if (ret < 0) {
|
|
dev_err(i2c->dev, "can not enable clock\n");
|
|
return ret;
|
|
}
|
|
pinctrl_pm_select_default_state(i2c->dev);
|
|
if (i2c->mode == I2C_IRQ_MODE)
|
|
enable_irq(i2c->irq);
|
|
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_HIBERNATION
|
|
static int meson_i2c_freeze(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct meson_i2c *i2c = (struct meson_i2c *)dev_get_drvdata(dev);
|
|
|
|
if (i2c->is_runtime_sleep)
|
|
return 0;
|
|
ret = meson_i2c_put(i2c);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int meson_i2c_thaw(struct device *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int meson_i2c_restore(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct meson_i2c *i2c = (struct meson_i2c *)dev_get_drvdata(dev);
|
|
|
|
if (i2c->is_runtime_sleep)
|
|
return 0;
|
|
ret = meson_i2c_regain(i2c);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
static int __maybe_unused meson_i2c_runtime_suspend(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct meson_i2c *i2c = (struct meson_i2c *)dev_get_drvdata(dev);
|
|
|
|
ret = meson_i2c_put(i2c);
|
|
i2c->is_runtime_sleep = true;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __maybe_unused meson_i2c_runtime_resume(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct meson_i2c *i2c = (struct meson_i2c *)dev_get_drvdata(dev);
|
|
|
|
ret = meson_i2c_regain(i2c);
|
|
i2c->is_runtime_sleep = false;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dev_pm_ops meson_i2c_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(meson_i2c_runtime_suspend,
|
|
meson_i2c_runtime_resume, NULL)
|
|
#ifdef CONFIG_HIBERNATION
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.freeze = meson_i2c_freeze,
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.thaw = meson_i2c_thaw,
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.restore = meson_i2c_restore,
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#endif
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};
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#endif
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static struct meson_i2c_data i2c_tee_data = {
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.tee = true,
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.enable_irq_bits = ENABLE_IRQ_BIT,
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.xfer_done_bits = TRANS_DONE,
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.xfer_err_bits = TRANS_ERROR,
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};
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static struct meson_i2c_data i2c_normal_data = {
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.tee = false,
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.enable_irq_bits = ENABLE_IRQ_BIT,
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.xfer_done_bits = TRANS_DONE,
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.xfer_err_bits = TRANS_ERROR,
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};
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static struct meson_i2c_data i2c_normal_a9 = {
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.tee = false,
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.enable_irq_bits = A9_ENABLE_IRQ_BIT,
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.xfer_done_bits = A9_TRANS_DONE,
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.xfer_err_bits = A9_TRANS_ERROR,
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};
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static const struct of_device_id meson_i2c_v2_match[] = {
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{ .compatible = "amlogic,meson-i2c-v2",
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.data = &i2c_normal_data
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},
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{
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.compatible = "amlogic,meson-tee-i2c-v2",
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.data = &i2c_tee_data
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},
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{ .compatible = "amlogic,meson-i2c-v2-1",
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.data = &i2c_normal_a9
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, meson_i2c_v2_match);
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static struct platform_driver meson_i2c_driver = {
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.probe = meson_i2c_probe,
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.remove = meson_i2c_remove,
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.driver = {
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.name = "meson-i2c-v2",
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.pm = &meson_i2c_pm_ops,
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.of_match_table = meson_i2c_v2_match,
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},
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};
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int __init i2c_meson_v2_init(void)
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{
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return platform_driver_register(&meson_i2c_driver);
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}
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void __exit i2c_meson_v2_exit(void)
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{
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platform_driver_unregister(&meson_i2c_driver);
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}
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MODULE_DESCRIPTION("Amlogic Meson I2C V2 Bus driver");
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MODULE_AUTHOR("Junyi Zhao <[email protected]>");
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MODULE_LICENSE("GPL v2");
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