1196 lines
32 KiB
C
1196 lines
32 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <[email protected]>
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Jerome Brunet <[email protected]>
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/amlogic/glb_timer.h>
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#include <linux/amlogic/irq_latch.h>
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#define NUM_CHANNEL 8
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#define MAX_INPUT_MUX 256
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#define REG_EDGE_POL 0x00
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#define REG_PIN_03_SEL 0x04
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#define REG_PIN_47_SEL 0x08
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#define REG_FILTER_SEL 0x0c
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/* use for A1 like chips */
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#define REG_PIN_A1_SEL 0x04
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/*
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* Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
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* bits 24 to 31. Tests on the actual HW show that these bits are
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* stuck at 0. Bits 8 to 15 are responsive and have the expected
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* effect.
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*/
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#define REG_EDGE_POL_EDGE(params, x) BIT((params)->edge_single_offset + (x))
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#define REG_EDGE_POL_LOW(params, x) BIT((params)->pol_low_offset + (x))
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#define REG_BOTH_EDGE(params, x) BIT((params)->edge_both_offset + (x))
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#define REG_EDGE_POL_MASK(params, x) ({ \
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typeof(params) __params = (params); \
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typeof(x) __x = (x); \
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REG_EDGE_POL_EDGE(__params, __x) | \
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REG_EDGE_POL_LOW(__params, __x) | \
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REG_BOTH_EDGE(__params, __x); })
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#define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
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#define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
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#ifdef CONFIG_AMLOGIC_MODIFY
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#define REG_PIN_SC2_SEL 0x04
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#define REG_EDGE_POL_EXTR 0x1c
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#define REG_EDGE_POL_MASK_SC2(x) \
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({typeof(x) _x = (x); BIT(_x) | BIT(12 + (_x)); })
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#endif
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struct meson_gpio_irq_controller;
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#ifndef CONFIG_AMLOGIC_ZAPPER_CUT
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static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
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unsigned int channel, unsigned long hwirq);
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static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl);
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#endif
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static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
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unsigned int channel,
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unsigned long hwirq);
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#ifdef CONFIG_AMLOGIC_MODIFY
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static unsigned int
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meson_sc2_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
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unsigned int idx, u32 val);
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#ifndef CONFIG_AMLOGIC_ZAPPER_CUT
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static unsigned int
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meson_p1_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
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unsigned int idx, u32 val);
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#endif
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#endif
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static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
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struct irq_ctl_ops {
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void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
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unsigned int channel, unsigned long hwirq);
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void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
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#ifdef CONFIG_AMLOGIC_MODIFY
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unsigned int (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl,
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unsigned int idx, u32 val);
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#endif
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};
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struct meson_gpio_irq_params {
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unsigned int nr_hwirq;
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bool support_edge_both;
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unsigned int edge_both_offset;
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unsigned int edge_single_offset;
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unsigned int pol_low_offset;
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unsigned int pin_sel_mask;
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struct irq_ctl_ops ops;
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#ifdef CONFIG_AMLOGIC_MODIFY
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unsigned int pin_sel_reg_base;
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unsigned int edge_sel_reg;
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unsigned int pol_low_sel_reg;
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unsigned int both_sel_reg;
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u8 channel_num;
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#endif
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};
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#ifndef CONFIG_AMLOGIC_MODIFY
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#define INIT_MESON_COMMON(irqs, init, sel) \
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.nr_hwirq = irqs, \
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.ops = { \
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.gpio_irq_init = init, \
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.gpio_irq_sel_pin = sel, \
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},
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#else
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#define INIT_MESON_COMMON(irqs, init, sel) \
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.nr_hwirq = irqs, \
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.channel_num = 8, \
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.ops = { \
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.gpio_irq_init = init, \
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.gpio_irq_sel_pin = sel, \
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},
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#define INIT_MESON_SC2_COMMON(irqs, init, sel, type) \
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.nr_hwirq = irqs, \
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.ops = { \
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.gpio_irq_init = init, \
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.gpio_irq_sel_pin = sel, \
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.gpio_irq_sel_type = type, \
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},
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#endif
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#ifndef CONFIG_AMLOGIC_ZAPPER_CUT
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#define INIT_MESON8_COMMON_DATA(irqs) \
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INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy, \
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meson8_gpio_irq_sel_pin) \
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.edge_single_offset = 0, \
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.pol_low_offset = 16, \
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.pin_sel_mask = 0xff, \
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#define INIT_MESON_A1_COMMON_DATA(irqs) \
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INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
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meson_a1_gpio_irq_sel_pin) \
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.support_edge_both = true, \
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.edge_both_offset = 16, \
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.edge_single_offset = 8, \
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.pol_low_offset = 0, \
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.pin_sel_reg_base = 0x04, \
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.pin_sel_mask = 0x7f, \
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#endif
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#ifdef CONFIG_AMLOGIC_MODIFY
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/* For sc2/t7 like platform */
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#define INIT_MESON_SC2_COMMON_DATA(irqs) \
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INIT_MESON_SC2_COMMON(irqs, meson_a1_gpio_irq_init, \
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meson_a1_gpio_irq_sel_pin, \
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meson_sc2_gpio_irq_sel_type) \
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.support_edge_both = true, \
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.edge_both_offset = 0, \
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.edge_single_offset = 12, \
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.pol_low_offset = 0, \
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.pin_sel_mask = 0xff, \
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.pin_sel_reg_base = 0x04, \
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.channel_num = 12,
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/* For a9 like platform */
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#define INIT_MESON_A9_COMMON_DATA(irqs) \
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INIT_MESON_SC2_COMMON(irqs, meson_a1_gpio_irq_init, \
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meson_a1_gpio_irq_sel_pin, \
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meson_sc2_gpio_irq_sel_type) \
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.support_edge_both = true, \
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.edge_both_offset = 0, \
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.edge_single_offset = 12, \
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.pol_low_offset = 0, \
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.pin_sel_mask = 0xff, \
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.pin_sel_reg_base = 0x04,
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#define INIT_MESON_A9_AO_COMMON_DATA(irqs) \
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INIT_MESON_SC2_COMMON(irqs, meson_a1_gpio_irq_init, \
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meson_a1_gpio_irq_sel_pin, \
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meson_p1_gpio_irq_sel_type) \
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.support_edge_both = true, \
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.edge_both_offset = 0, \
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.edge_single_offset = 0, \
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.pol_low_offset = 0, \
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.pin_sel_mask = 0xff, \
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.pin_sel_reg_base = 0x04, \
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.edge_sel_reg = 0x30, \
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.pol_low_sel_reg = 0x00, \
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.both_sel_reg = 0x2c,
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#ifndef CONFIG_AMLOGIC_ZAPPER_CUT
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#define INIT_MESON_P1_COMMON_DATA(irqs) \
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INIT_MESON_SC2_COMMON(irqs, meson_a1_gpio_irq_init, \
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meson_a1_gpio_irq_sel_pin, \
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meson_p1_gpio_irq_sel_type) \
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.support_edge_both = true, \
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.edge_both_offset = 0, \
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.edge_single_offset = 0, \
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.pol_low_offset = 0, \
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.pin_sel_mask = 0xff, \
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.pin_sel_reg_base = 0x10, \
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.edge_sel_reg = 0x04, \
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.pol_low_sel_reg = 0x08, \
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.both_sel_reg = 0x0c, \
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.channel_num = 32,
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#define INIT_MESON_A4_AO_COMMON_DATA(irqs) \
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INIT_MESON_SC2_COMMON(irqs, meson_a1_gpio_irq_init, \
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meson_a1_gpio_irq_sel_pin, \
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meson_p1_gpio_irq_sel_type) \
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.support_edge_both = true, \
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.edge_both_offset = 0, \
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.edge_single_offset = 12, \
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.pol_low_offset = 0, \
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.pin_sel_mask = 0xff, \
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.pin_sel_reg_base = 0x04, \
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.edge_sel_reg = 0x00, \
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.pol_low_sel_reg = 0x00, \
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.both_sel_reg = 0x08, \
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.channel_num = 2,
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#define INIT_MESON_C4_AO_COMMON_DATA(irqs) \
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INIT_MESON_SC2_COMMON(irqs, meson_a1_gpio_irq_init, \
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meson_a1_gpio_irq_sel_pin, \
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meson_p1_gpio_irq_sel_type) \
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.support_edge_both = true, \
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.edge_both_offset = 16, \
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.edge_single_offset = 12, \
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.pol_low_offset = 0, \
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.pin_sel_mask = 0xff, \
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.pin_sel_reg_base = 0x04, \
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.edge_sel_reg = 0x00, \
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.pol_low_sel_reg = 0x00, \
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.both_sel_reg = 0x14, \
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.channel_num = 9,
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#define INIT_MESON_C5_AO_COMMON_DATA(irqs) \
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INIT_MESON_SC2_COMMON(irqs, meson_a1_gpio_irq_init, \
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meson_a1_gpio_irq_sel_pin, \
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meson_p1_gpio_irq_sel_type) \
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.support_edge_both = true, \
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.edge_both_offset = 0, \
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.edge_single_offset = 0, \
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.pol_low_offset = 0, \
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.pin_sel_mask = 0xff, \
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.pin_sel_reg_base = 0x04, \
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.edge_sel_reg = 0x30, \
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.pol_low_sel_reg = 0x00, \
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.both_sel_reg = 0x2c, \
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.channel_num = 20,
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#endif
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#endif
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#ifndef CONFIG_AMLOGIC_REMOVE_OLD
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static const struct meson_gpio_irq_params meson8_params = {
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INIT_MESON8_COMMON_DATA(134)
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};
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static const struct meson_gpio_irq_params meson8b_params = {
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INIT_MESON8_COMMON_DATA(119)
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};
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static const struct meson_gpio_irq_params gxbb_params = {
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INIT_MESON8_COMMON_DATA(133)
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};
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static const struct meson_gpio_irq_params gxl_params = {
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INIT_MESON8_COMMON_DATA(110)
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};
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#endif
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#ifndef CONFIG_AMLOGIC_ZAPPER_CUT
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static const struct meson_gpio_irq_params a1_params = {
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INIT_MESON_A1_COMMON_DATA(62)
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};
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static const struct meson_gpio_irq_params axg_params = {
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INIT_MESON8_COMMON_DATA(100)
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};
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static const struct meson_gpio_irq_params sm1_params = {
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INIT_MESON8_COMMON_DATA(100)
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.support_edge_both = true,
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.edge_both_offset = 8,
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};
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#endif
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#ifdef CONFIG_AMLOGIC_MODIFY
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#ifndef CONFIG_AMLOGIC_ZAPPER_CUT
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static const struct meson_gpio_irq_params tm2_params = {
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INIT_MESON8_COMMON_DATA(104)
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.support_edge_both = true,
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.edge_both_offset = 8,
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};
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static const struct meson_gpio_irq_params sc2_params = {
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INIT_MESON_SC2_COMMON_DATA(87)
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};
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static const struct meson_gpio_irq_params t5d_params = {
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INIT_MESON8_COMMON_DATA(113)
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.support_edge_both = true,
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.edge_both_offset = 8,
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};
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static const struct meson_gpio_irq_params t7_params = {
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INIT_MESON_SC2_COMMON_DATA(157)
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};
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#endif
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#ifndef CONFIG_AMLOGIC_ZAPPER_CUT_C1A
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static const struct meson_gpio_irq_params s4_params = {
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INIT_MESON_SC2_COMMON_DATA(82)
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};
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#endif
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#ifndef CONFIG_AMLOGIC_ZAPPER_CUT
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static const struct meson_gpio_irq_params t3_params = {
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INIT_MESON_SC2_COMMON_DATA(139)
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};
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static const struct meson_gpio_irq_params p1_params = {
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INIT_MESON_P1_COMMON_DATA(230)
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};
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static const struct meson_gpio_irq_params t5w_params = {
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INIT_MESON8_COMMON_DATA(130)
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.support_edge_both = true,
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.edge_both_offset = 8,
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};
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static const struct meson_gpio_irq_params c2_params = {
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INIT_MESON_A1_COMMON_DATA(90)
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};
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static const struct meson_gpio_irq_params c3_params = {
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INIT_MESON_SC2_COMMON_DATA(55)
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};
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static const struct meson_gpio_irq_params t5m_params = {
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INIT_MESON_SC2_COMMON_DATA(149)
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};
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static const struct meson_gpio_irq_params s5_params = {
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INIT_MESON_P1_COMMON_DATA(118)
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};
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static const struct meson_gpio_irq_params t3x_params = {
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INIT_MESON_SC2_COMMON_DATA(151)
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};
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static const struct meson_gpio_irq_params txhd2_params = {
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INIT_MESON8_COMMON_DATA(80)
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.support_edge_both = true,
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.edge_both_offset = 8,
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};
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static const struct meson_gpio_irq_params s7_params = {
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INIT_MESON_SC2_COMMON_DATA(84)
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};
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static const struct meson_gpio_irq_params s6_params = {
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INIT_MESON_SC2_COMMON_DATA(101)
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};
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static const struct meson_gpio_irq_params t6d_params = {
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INIT_MESON_SC2_COMMON_DATA(131)
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};
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static const struct meson_gpio_irq_params t6w_params = {
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INIT_MESON_SC2_COMMON_DATA(142)
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};
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static const struct meson_gpio_irq_params t6x_params = {
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INIT_MESON_SC2_COMMON_DATA(154)
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};
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static const struct meson_gpio_irq_params c4_params = {
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INIT_MESON_SC2_COMMON_DATA(55)
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};
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static const struct meson_gpio_irq_params c4_ao_params = {
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INIT_MESON_C4_AO_COMMON_DATA(15)
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};
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#endif // end of ifndef CONFIG_AMLOGIC_ZAPPER_CUT
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static const struct meson_gpio_irq_params s1a_params = {
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INIT_MESON_SC2_COMMON_DATA(40)
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};
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static const struct meson_gpio_irq_params a4_params = {
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INIT_MESON_SC2_COMMON_DATA(81)
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};
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static const struct meson_gpio_irq_params a4_ao_params = {
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INIT_MESON_A4_AO_COMMON_DATA(8)
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};
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static const struct meson_gpio_irq_params a5_params = {
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INIT_MESON_SC2_COMMON_DATA(99)
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};
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static const struct meson_gpio_irq_params a9_params = {
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INIT_MESON_A9_COMMON_DATA(96)
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};
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static const struct meson_gpio_irq_params a9_ao_params = {
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INIT_MESON_A9_AO_COMMON_DATA(39)
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};
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static const struct meson_gpio_irq_params c5_params = {
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INIT_MESON_SC2_COMMON_DATA(109)
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};
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static const struct meson_gpio_irq_params c5_ao_params = {
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INIT_MESON_C5_AO_COMMON_DATA(48)
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};
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#endif //end of CONFIG_AMLOGIC_MODIFY
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static const struct of_device_id meson_irq_gpio_matches[] = {
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#ifndef CONFIG_AMLOGIC_REMOVE_OLD
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{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
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{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
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{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
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{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
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{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
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#endif
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#ifndef CONFIG_AMLOGIC_ZAPPER_CUT
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{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
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{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
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{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
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#endif
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#ifdef CONFIG_AMLOGIC_MODIFY
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#ifndef CONFIG_AMLOGIC_ZAPPER_CUT
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{ .compatible = "amlogic,meson-tm2-gpio-intc", .data = &tm2_params },
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{ .compatible = "amlogic,meson-sc2-gpio-intc", .data = &sc2_params },
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{ .compatible = "amlogic,meson-t5d-gpio-intc", .data = &t5d_params },
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{ .compatible = "amlogic,meson-t7-gpio-intc", .data = &t7_params },
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#endif
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#ifndef CONFIG_AMLOGIC_ZAPPER_CUT_C1A
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{ .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
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#endif
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#ifndef CONFIG_AMLOGIC_ZAPPER_CUT
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{ .compatible = "amlogic,meson-t3-gpio-intc", .data = &t3_params },
|
|
{ .compatible = "amlogic,meson-p1-gpio-intc", .data = &p1_params },
|
|
{ .compatible = "amlogic,meson-t5w-gpio-intc", .data = &t5w_params },
|
|
{ .compatible = "amlogic,meson-c1-gpio-intc", .data = &c2_params },
|
|
{ .compatible = "amlogic,meson-c2-gpio-intc", .data = &c2_params },
|
|
{ .compatible = "amlogic,meson-c3-gpio-intc", .data = &c3_params },
|
|
{ .compatible = "amlogic,meson-c5-gpio-intc", .data = &c5_params },
|
|
{ .compatible = "amlogic,meson-c5-gpio-ao-intc", .data = &c5_ao_params },
|
|
{ .compatible = "amlogic,meson-t5m-gpio-intc", .data = &t5m_params },
|
|
{ .compatible = "amlogic,meson-s5-gpio-intc", .data = &s5_params },
|
|
{ .compatible = "amlogic,meson-t3x-gpio-intc", .data = &t3x_params },
|
|
{ .compatible = "amlogic,meson-txhd2-gpio-intc", .data = &txhd2_params },
|
|
{ .compatible = "amlogic,meson-s7-gpio-intc", .data = &s7_params },
|
|
{ .compatible = "amlogic,meson-s6-gpio-intc", .data = &s6_params },
|
|
{ .compatible = "amlogic,meson-t6d-gpio-intc", .data = &t6d_params },
|
|
{ .compatible = "amlogic,meson-t6w-gpio-intc", .data = &t6w_params },
|
|
{ .compatible = "amlogic,meson-t6x-gpio-intc", .data = &t6x_params },
|
|
{ .compatible = "amlogic,meson-c4-gpio-intc", .data = &c4_params },
|
|
{ .compatible = "amlogic,meson-c4-gpio-ao-intc", .data = &c4_ao_params },
|
|
#endif // end of ifndef CONFIG_AMLOGIC_ZAPPER_CUT
|
|
{ .compatible = "amlogic,meson-s1a-gpio-intc", .data = &s1a_params },
|
|
{ .compatible = "amlogic,meson-a4-gpio-intc", .data = &a4_params },
|
|
{ .compatible = "amlogic,meson-a4-gpio-ao-intc", .data = &a4_ao_params },
|
|
{ .compatible = "amlogic,meson-a5-gpio-intc", .data = &a5_params },
|
|
{ .compatible = "amlogic,meson-a9-gpio-intc", .data = &a9_params },
|
|
{ .compatible = "amlogic,meson-a9-gpio-ao-intc", .data = &a9_ao_params },
|
|
#endif // end of CONFIG_AMLOGIC_MODIFY
|
|
{ }
|
|
};
|
|
|
|
struct meson_gpio_irq_controller {
|
|
const struct meson_gpio_irq_params *params;
|
|
void __iomem *base;
|
|
#ifndef CONFIG_AMLOGIC_MODIFY
|
|
u32 channel_irqs[NUM_CHANNEL];
|
|
DECLARE_BITMAP(channel_map, NUM_CHANNEL);
|
|
#else
|
|
u32 *channel_irqs;
|
|
unsigned long *channel_map;
|
|
u8 channel_num;
|
|
u32 *shadow;
|
|
int shadow_size;
|
|
bool level_high_to_gic;
|
|
bool save_register;
|
|
#endif
|
|
raw_spinlock_t lock; //
|
|
};
|
|
|
|
static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
|
|
unsigned int reg, u32 mask, u32 val)
|
|
{
|
|
u32 tmp;
|
|
|
|
tmp = readl_relaxed(ctl->base + reg);
|
|
tmp &= ~mask;
|
|
tmp |= val;
|
|
writel_relaxed(tmp, ctl->base + reg);
|
|
}
|
|
|
|
#ifndef CONFIG_AMLOGIC_ZAPPER_CUT
|
|
static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl)
|
|
{
|
|
}
|
|
|
|
static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
|
|
unsigned int channel, unsigned long hwirq)
|
|
{
|
|
unsigned int reg_offset;
|
|
unsigned int bit_offset;
|
|
|
|
reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
|
|
bit_offset = REG_PIN_SEL_SHIFT(channel);
|
|
|
|
meson_gpio_irq_update_bits(ctl, reg_offset,
|
|
ctl->params->pin_sel_mask << bit_offset,
|
|
hwirq << bit_offset);
|
|
}
|
|
#endif
|
|
|
|
static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
|
|
unsigned int channel,
|
|
unsigned long hwirq)
|
|
{
|
|
unsigned int reg_offset;
|
|
unsigned int bit_offset;
|
|
|
|
bit_offset = ((channel % 2) == 0) ? 0 : 16;
|
|
#ifndef CONFIG_AMLOGIC_MODIFY
|
|
reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2);
|
|
#else
|
|
reg_offset = ctl->params->pin_sel_reg_base + ((channel / 2) << 2);
|
|
#endif
|
|
|
|
meson_gpio_irq_update_bits(ctl, reg_offset,
|
|
ctl->params->pin_sel_mask << bit_offset,
|
|
hwirq << bit_offset);
|
|
}
|
|
|
|
/* For a1 or later chips like a1 there is a switch to enable/disable irq */
|
|
static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl)
|
|
{
|
|
meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31));
|
|
}
|
|
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
static unsigned int
|
|
meson_sc2_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
|
|
unsigned int idx, unsigned int type)
|
|
{
|
|
unsigned int val = 0;
|
|
unsigned long flags;
|
|
|
|
meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_EXTR, BIT(0 + (idx)), 0);
|
|
|
|
if (type == IRQ_TYPE_EDGE_BOTH) {
|
|
val |= BIT(ctl->params->edge_both_offset + (idx));
|
|
raw_spin_lock_irqsave(&ctl->lock, flags);
|
|
meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_EXTR,
|
|
BIT(ctl->params->edge_both_offset + (idx)), val);
|
|
raw_spin_unlock_irqrestore(&ctl->lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
raw_spin_lock_irqsave(&ctl->lock, flags);
|
|
|
|
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
|
|
val |= BIT(ctl->params->pol_low_offset + (idx));
|
|
|
|
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
|
|
val |= BIT(ctl->params->edge_single_offset + (idx));
|
|
|
|
meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
|
|
REG_EDGE_POL_MASK_SC2(idx), val);
|
|
|
|
raw_spin_unlock_irqrestore(&ctl->lock, flags);
|
|
|
|
return 0;
|
|
};
|
|
|
|
#ifndef CONFIG_AMLOGIC_ZAPPER_CUT
|
|
static unsigned int
|
|
meson_p1_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
|
|
unsigned int idx, unsigned int type)
|
|
{
|
|
unsigned int val = 0;
|
|
unsigned long flags;
|
|
const struct meson_gpio_irq_params *params;
|
|
|
|
params = ctl->params;
|
|
|
|
meson_gpio_irq_update_bits(ctl, params->both_sel_reg, BIT(0 + (idx)), 0);
|
|
|
|
if (type == IRQ_TYPE_EDGE_BOTH) {
|
|
val |= BIT(params->edge_both_offset + (idx));
|
|
raw_spin_lock_irqsave(&ctl->lock, flags);
|
|
meson_gpio_irq_update_bits(ctl, params->both_sel_reg,
|
|
BIT(params->edge_both_offset + (idx)), val);
|
|
raw_spin_unlock_irqrestore(&ctl->lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
raw_spin_lock_irqsave(&ctl->lock, flags);
|
|
|
|
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
|
|
val = 0;
|
|
val |= BIT(params->pol_low_offset + (idx));
|
|
meson_gpio_irq_update_bits(ctl, params->pol_low_sel_reg, BIT(idx), val);
|
|
}
|
|
|
|
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
|
|
val = 0;
|
|
val |= BIT(params->edge_single_offset + (idx));
|
|
meson_gpio_irq_update_bits(ctl, params->edge_sel_reg, BIT(idx), val);
|
|
}
|
|
|
|
raw_spin_unlock_irqrestore(&ctl->lock, flags);
|
|
|
|
return 0;
|
|
};
|
|
#endif
|
|
#endif
|
|
|
|
static int
|
|
meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
|
|
unsigned long hwirq,
|
|
u32 **channel_hwirq)
|
|
{
|
|
unsigned int idx;
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
unsigned long flags;
|
|
#endif
|
|
|
|
#ifndef CONFIG_AMLOGIC_MODIFY
|
|
raw_spin_lock(&ctl->lock);
|
|
#else
|
|
raw_spin_lock_irqsave(&ctl->lock, flags);
|
|
#endif
|
|
/* Find a free channel */
|
|
#ifndef CONFIG_AMLOGIC_MODIFY
|
|
idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
|
|
if (idx >= NUM_CHANNEL) {
|
|
raw_spin_unlock(&ctl->lock);
|
|
#else
|
|
idx = find_first_zero_bit(ctl->channel_map, ctl->channel_num);
|
|
if (idx >= ctl->channel_num) {
|
|
raw_spin_unlock_irqrestore(&ctl->lock, flags);
|
|
#endif
|
|
pr_err("No channel available\n");
|
|
return -ENOSPC;
|
|
}
|
|
|
|
/* Mark the channel as used */
|
|
set_bit(idx, ctl->channel_map);
|
|
|
|
/*
|
|
* Setup the mux of the channel to route the signal of the pad
|
|
* to the appropriate input of the GIC
|
|
*/
|
|
ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq);
|
|
|
|
/*
|
|
* Get the hwirq number assigned to this channel through
|
|
* a pointer the channel_irq table. The added benifit of this
|
|
* method is that we can also retrieve the channel index with
|
|
* it, using the table base.
|
|
*/
|
|
*channel_hwirq = &ctl->channel_irqs[idx];
|
|
|
|
#ifndef CONFIG_AMLOGIC_MODIFY
|
|
raw_spin_unlock(&ctl->lock);
|
|
#else
|
|
raw_spin_unlock_irqrestore(&ctl->lock, flags);
|
|
#endif
|
|
|
|
pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
|
|
hwirq, idx, **channel_hwirq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned int
|
|
meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
|
|
u32 *channel_hwirq)
|
|
{
|
|
return channel_hwirq - ctl->channel_irqs;
|
|
}
|
|
|
|
static void
|
|
meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
|
|
u32 *channel_hwirq)
|
|
{
|
|
unsigned int idx;
|
|
|
|
idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
|
|
clear_bit(idx, ctl->channel_map);
|
|
}
|
|
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
unsigned int gpio_irq_get_channel_idx(int irq, u32 *hwirq)
|
|
{
|
|
struct irq_desc *desc;
|
|
struct irq_data *data;
|
|
struct meson_gpio_irq_controller *ctl;
|
|
u32 *channel_hwirq;
|
|
|
|
desc = irq_to_desc(irq);
|
|
if (IS_ERR_OR_NULL(desc)) {
|
|
pr_err("%s: can't get irq desc\n", __func__);
|
|
return 0xffff;
|
|
}
|
|
|
|
data = irq_desc_get_irq_data(desc);
|
|
ctl = data->domain->host_data;
|
|
|
|
channel_hwirq = irq_data_get_irq_chip_data(data);
|
|
*hwirq = *channel_hwirq;
|
|
|
|
return meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
|
|
}
|
|
EXPORT_SYMBOL_GPL(gpio_irq_get_channel_idx);
|
|
#endif
|
|
|
|
static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
|
|
unsigned int type,
|
|
u32 *channel_hwirq)
|
|
{
|
|
u32 val = 0;
|
|
unsigned int idx;
|
|
const struct meson_gpio_irq_params *params;
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
unsigned long flags;
|
|
#endif
|
|
|
|
params = ctl->params;
|
|
idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
|
|
|
|
/*
|
|
* The controller has a filter block to operate in either LEVEL or
|
|
* EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
|
|
* EDGE_FALLING support (which the GIC does not support), the filter
|
|
* block is also able to invert the input signal it gets before
|
|
* providing it to the GIC.
|
|
*/
|
|
type &= IRQ_TYPE_SENSE_MASK;
|
|
|
|
/*
|
|
* New controller support EDGE_BOTH trigger. This setting takes
|
|
* precedence over the other edge/polarity settings
|
|
*/
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
if (params->ops.gpio_irq_sel_type)
|
|
return params->ops.gpio_irq_sel_type(ctl, idx, type);
|
|
#endif
|
|
if (type == IRQ_TYPE_EDGE_BOTH) {
|
|
if (!params->support_edge_both)
|
|
return -EINVAL;
|
|
|
|
val |= REG_BOTH_EDGE(params, idx);
|
|
} else {
|
|
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
|
|
val |= REG_EDGE_POL_EDGE(params, idx);
|
|
|
|
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
|
|
val |= REG_EDGE_POL_LOW(params, idx);
|
|
}
|
|
|
|
#ifndef CONFIG_AMLOGIC_MODIFY
|
|
raw_spin_lock(&ctl->lock);
|
|
#else
|
|
raw_spin_lock_irqsave(&ctl->lock, flags);
|
|
#endif
|
|
|
|
meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
|
|
REG_EDGE_POL_MASK(params, idx), val);
|
|
|
|
#ifndef CONFIG_AMLOGIC_MODIFY
|
|
raw_spin_unlock(&ctl->lock);
|
|
#else
|
|
raw_spin_unlock_irqrestore(&ctl->lock, flags);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned int meson_gpio_irq_type_output(unsigned int type)
|
|
{
|
|
unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
|
|
|
|
type &= ~IRQ_TYPE_SENSE_MASK;
|
|
|
|
/*
|
|
* The polarity of the signal provided to the GIC should always
|
|
* be high.
|
|
*/
|
|
if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
|
|
type |= IRQ_TYPE_LEVEL_HIGH;
|
|
else
|
|
type |= IRQ_TYPE_EDGE_RISING;
|
|
|
|
return type;
|
|
}
|
|
|
|
static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
|
|
{
|
|
struct meson_gpio_irq_controller *ctl = data->domain->host_data;
|
|
u32 *channel_hwirq = irq_data_get_irq_chip_data(data);
|
|
int ret;
|
|
|
|
ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (ctl->level_high_to_gic) {
|
|
type &= ~IRQ_TYPE_SENSE_MASK;
|
|
type |= IRQ_TYPE_LEVEL_HIGH;
|
|
irq_latch_clr(data->irq);
|
|
return irq_chip_set_type_parent(data, type);
|
|
} else {
|
|
return irq_chip_set_type_parent(data,
|
|
meson_gpio_irq_type_output(type));
|
|
}
|
|
}
|
|
|
|
static struct irq_chip meson_gpio_irq_chip = {
|
|
.name = "meson-gpio-irqchip",
|
|
.irq_mask = irq_chip_mask_parent,
|
|
.irq_unmask = irq_chip_unmask_parent,
|
|
.irq_eoi = irq_chip_eoi_parent,
|
|
.irq_set_type = meson_gpio_irq_set_type,
|
|
.irq_retrigger = irq_chip_retrigger_hierarchy,
|
|
#ifdef CONFIG_SMP
|
|
.irq_set_affinity = irq_chip_set_affinity_parent,
|
|
#endif
|
|
.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE,
|
|
};
|
|
|
|
static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
|
|
struct irq_fwspec *fwspec,
|
|
unsigned long *hwirq,
|
|
unsigned int *type)
|
|
{
|
|
if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
|
|
*hwirq = fwspec->param[0];
|
|
*type = fwspec->param[1];
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
|
|
unsigned int virq,
|
|
u32 hwirq,
|
|
unsigned int type)
|
|
{
|
|
struct irq_fwspec fwspec;
|
|
struct meson_gpio_irq_controller *ctl = domain->host_data;
|
|
|
|
fwspec.fwnode = domain->parent->fwnode;
|
|
fwspec.param_count = 3;
|
|
fwspec.param[0] = 0; /* SPI */
|
|
fwspec.param[1] = hwirq;
|
|
|
|
if (ctl->level_high_to_gic) {
|
|
type &= ~IRQ_TYPE_SENSE_MASK;
|
|
type |= IRQ_TYPE_LEVEL_HIGH;
|
|
fwspec.param[2] = type;
|
|
} else {
|
|
fwspec.param[2] = meson_gpio_irq_type_output(type);
|
|
}
|
|
|
|
return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
|
|
}
|
|
|
|
static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
|
|
unsigned int virq,
|
|
unsigned int nr_irqs,
|
|
void *data)
|
|
{
|
|
struct irq_fwspec *fwspec = data;
|
|
struct meson_gpio_irq_controller *ctl = domain->host_data;
|
|
unsigned long hwirq;
|
|
u32 *channel_hwirq;
|
|
unsigned int type;
|
|
int ret;
|
|
|
|
if (WARN_ON(nr_irqs != 1))
|
|
return -EINVAL;
|
|
|
|
ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
|
|
*channel_hwirq, type);
|
|
if (ret < 0) {
|
|
pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
|
|
meson_gpio_irq_release_channel(ctl, channel_hwirq);
|
|
return ret;
|
|
}
|
|
|
|
irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
|
|
&meson_gpio_irq_chip, channel_hwirq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void meson_gpio_irq_domain_free(struct irq_domain *domain,
|
|
unsigned int virq,
|
|
unsigned int nr_irqs)
|
|
{
|
|
struct meson_gpio_irq_controller *ctl = domain->host_data;
|
|
struct irq_data *irq_data;
|
|
u32 *channel_hwirq;
|
|
|
|
if (WARN_ON(nr_irqs != 1))
|
|
return;
|
|
|
|
irq_domain_free_irqs_parent(domain, virq, 1);
|
|
|
|
irq_data = irq_domain_get_irq_data(domain, virq);
|
|
channel_hwirq = irq_data_get_irq_chip_data(irq_data);
|
|
|
|
meson_gpio_irq_release_channel(ctl, channel_hwirq);
|
|
}
|
|
|
|
static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
|
|
.alloc = meson_gpio_irq_domain_alloc,
|
|
.free = meson_gpio_irq_domain_free,
|
|
.translate = meson_gpio_irq_domain_translate,
|
|
};
|
|
|
|
static int meson_gpio_irq_parse_dt(struct device_node *node,
|
|
struct meson_gpio_irq_controller *ctl)
|
|
{
|
|
const struct of_device_id *match;
|
|
int ret;
|
|
|
|
match = of_match_node(meson_irq_gpio_matches, node);
|
|
if (!match)
|
|
return -ENODEV;
|
|
|
|
ctl->params = match->data;
|
|
|
|
#ifndef CONFIG_AMLOGIC_MODIFY
|
|
ret = of_property_read_variable_u32_array(node,
|
|
"amlogic,channel-interrupts",
|
|
ctl->channel_irqs,
|
|
NUM_CHANNEL,
|
|
NUM_CHANNEL);
|
|
if (ret < 0) {
|
|
pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
|
|
return ret;
|
|
}
|
|
#else
|
|
ctl->channel_num = ctl->params->channel_num;
|
|
if (!ctl->channel_num) {
|
|
ret = of_property_count_u32_elems(node, "amlogic,channel-interrupts");
|
|
if (ret <= 0) {
|
|
pr_err("unable to read the number of %pOFP\n", node);
|
|
return -EINVAL;
|
|
}
|
|
ctl->channel_num = (u8)ret;
|
|
}
|
|
|
|
ctl->channel_irqs = kcalloc(ctl->channel_num,
|
|
sizeof(*ctl->channel_irqs), GFP_KERNEL);
|
|
ctl->channel_map = bitmap_zalloc(ctl->channel_num, GFP_KERNEL);
|
|
|
|
if (!ctl->channel_irqs || !ctl->channel_map) {
|
|
pr_err("allocate irqs and channel maps mem fail\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ret = of_property_read_variable_u32_array(node,
|
|
"amlogic,channel-interrupts",
|
|
ctl->channel_irqs,
|
|
ctl->channel_num,
|
|
ctl->channel_num);
|
|
if (ret < 0) {
|
|
pr_err("can't get %d channel interrupts\n", ctl->channel_num);
|
|
kfree(ctl->channel_irqs);
|
|
ctl->channel_irqs = NULL;
|
|
bitmap_free(ctl->channel_map);
|
|
ctl->channel_map = NULL;
|
|
return ret;
|
|
}
|
|
ret = of_property_read_bool(node, "amlogic,level-high-to-gic");
|
|
if (ret)
|
|
ctl->level_high_to_gic = true;
|
|
|
|
ret = of_property_read_bool(node, "amlogic,save-register");
|
|
if (ret)
|
|
ctl->save_register = true;
|
|
#endif
|
|
|
|
ctl->params->ops.gpio_irq_init(ctl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_AMLOGIC_MODIFY)
|
|
static int meson_gpio_irq_probe(struct platform_device *pdev)
|
|
#else
|
|
static int meson_gpio_irq_of_init(struct device_node *node,
|
|
struct device_node *parent)
|
|
#endif /* CONFIG_AMLOGIC_MODIFY */
|
|
{
|
|
struct irq_domain *domain, *parent_domain;
|
|
struct meson_gpio_irq_controller *ctl;
|
|
int ret;
|
|
#if defined(CONFIG_AMLOGIC_MODIFY)
|
|
struct device *irq_dev = &pdev->dev;
|
|
struct device_node *node = irq_dev->of_node;
|
|
struct device_node *parent = of_irq_find_parent(node);
|
|
struct resource res;
|
|
resource_size_t res_size;
|
|
#endif /* CONFIG_AMLOGIC_MODIFY */
|
|
|
|
if (!parent) {
|
|
pr_err("missing parent interrupt node\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
parent_domain = irq_find_host(parent);
|
|
if (!parent_domain) {
|
|
pr_err("unable to obtain parent domain\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
|
|
if (!ctl)
|
|
return -ENOMEM;
|
|
|
|
raw_spin_lock_init(&ctl->lock);
|
|
|
|
ctl->base = of_iomap(node, 0);
|
|
if (!ctl->base) {
|
|
ret = -ENOMEM;
|
|
goto free_ctl;
|
|
}
|
|
|
|
ret = meson_gpio_irq_parse_dt(node, ctl);
|
|
if (ret)
|
|
goto free_channel_irqs;
|
|
|
|
domain = irq_domain_create_hierarchy(parent_domain, 0,
|
|
ctl->params->nr_hwirq,
|
|
of_node_to_fwnode(node),
|
|
&meson_gpio_irq_domain_ops,
|
|
ctl);
|
|
if (!domain) {
|
|
pr_err("failed to add domain\n");
|
|
ret = -ENODEV;
|
|
goto free_channel_irqs;
|
|
}
|
|
#ifndef CONFIG_AMLOGIC_MODIFY
|
|
pr_info("%d to %d gpio interrupt mux initialized\n",
|
|
ctl->params->nr_hwirq, NUM_CHANNEL);
|
|
#else
|
|
pr_info("%d to %d gpio interrupt mux initialized\n",
|
|
ctl->params->nr_hwirq, ctl->channel_num);
|
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_AMLOGIC_MODIFY)
|
|
ret = of_address_to_resource(node, 0, &res);
|
|
if (ret)
|
|
goto free_channel_irqs;
|
|
res_size = resource_size(&res);
|
|
dev_dbg(irq_dev, "resource size: %d\n", (int)res_size);
|
|
if (res_size & 0x3)
|
|
dev_warn(irq_dev, "resource size is not a multiple of 4byte\n");
|
|
|
|
ctl->shadow = devm_kmalloc(irq_dev, res_size, GFP_KERNEL);
|
|
if (!ctl->shadow) {
|
|
ret = -ENOMEM;
|
|
goto free_channel_irqs;
|
|
}
|
|
ctl->shadow_size = res_size;
|
|
|
|
platform_set_drvdata(pdev, ctl);
|
|
#endif /* CONFIG_AMLOGIC_MODIFY */
|
|
|
|
return 0;
|
|
|
|
free_channel_irqs:
|
|
iounmap(ctl->base);
|
|
free_ctl:
|
|
kfree(ctl);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#if !defined(CONFIG_AMLOGIC_MODIFY)
|
|
static int meson_gpio_irq_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct device_node *parent = of_irq_find_parent(np);
|
|
|
|
return meson_gpio_irq_of_init(np, parent);
|
|
}
|
|
#endif /* CONFIG_AMLOGIC_MODIFY */
|
|
|
|
#if defined(CONFIG_AMLOGIC_MODIFY)
|
|
static int meson_gpio_irq_restore(struct device *dev)
|
|
{
|
|
struct meson_gpio_irq_controller *ctl = dev_get_drvdata(dev);
|
|
int index;
|
|
|
|
for (index = 0; index < ctl->shadow_size; index += 4)
|
|
writel_relaxed(ctl->shadow[index >> 2], ctl->base + index);
|
|
|
|
dev_dbg(dev, "restore register completed\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int meson_gpio_irq_freeze(struct device *dev)
|
|
{
|
|
struct meson_gpio_irq_controller *ctl = dev_get_drvdata(dev);
|
|
int index;
|
|
|
|
for (index = 0; index < ctl->shadow_size; index += 4)
|
|
ctl->shadow[index >> 2] = readl_relaxed(ctl->base + index);
|
|
|
|
dev_dbg(dev, "save register completed\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int meson_gpio_irq_suspend(struct device *dev)
|
|
{
|
|
struct meson_gpio_irq_controller *ctl = dev_get_drvdata(dev);
|
|
|
|
if (ctl->save_register)
|
|
meson_gpio_irq_freeze(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int meson_gpio_irq_resume(struct device *dev)
|
|
{
|
|
struct meson_gpio_irq_controller *ctl = dev_get_drvdata(dev);
|
|
|
|
if (ctl->save_register)
|
|
meson_gpio_irq_restore(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops meson_gpio_irq_pm_ops = {
|
|
.freeze = meson_gpio_irq_freeze,
|
|
.restore = meson_gpio_irq_restore,
|
|
.suspend = meson_gpio_irq_suspend,
|
|
.resume = meson_gpio_irq_resume,
|
|
};
|
|
#endif /* CONFIG_AMLOGIC_MODIFY */
|
|
|
|
static const struct of_device_id meson_gpio_irq_match_table[] = {
|
|
{ .compatible = "amlogic,meson-gpio-intc" },
|
|
{ .compatible = "amlogic,meson-gpio-ao-intc" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, meson_gpio_irq_match_table);
|
|
|
|
static struct platform_driver meson_gpio_irq_driver = {
|
|
.probe = meson_gpio_irq_probe,
|
|
.driver = {
|
|
.name = "meson_gpio_irq",
|
|
#if defined(CONFIG_AMLOGIC_MODIFY)
|
|
.pm = &meson_gpio_irq_pm_ops,
|
|
#endif /* CONFIG_AMLOGIC_MODIFY */
|
|
.of_match_table = meson_gpio_irq_match_table,
|
|
},
|
|
};
|
|
|
|
int __init meson_gpio_irq_init(void)
|
|
{
|
|
return platform_driver_register(&meson_gpio_irq_driver);
|
|
}
|
|
|
|
void __exit meson_gpio_irq_exit(void)
|
|
{
|
|
platform_driver_unregister(&meson_gpio_irq_driver);
|
|
}
|