206 lines
13 KiB
C
206 lines
13 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __TXHD2_H
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#define __TXHD2_H
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int txhd2_init(void);
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void txhd2_exit(void);
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int txhd2_aoclk_init(void);
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void txhd2_aoclk_exit(void);
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/* basic clk: 0xff646000 */
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#define HHI_CHECK_CLK_RESULT (0x004 << 2)
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#define HHI_DEMOD_32K_CNTL0 (0x010 << 2)
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#define HHI_DEMOD_32K_CNTL1 (0x011 << 2)
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#define HHI_VIID_CLK_DIV (0x04a << 2)
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#define HHI_VIID_CLK_CNTL (0x04b << 2)
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#define HHI_VID_CLK_DIV (0x059 << 2)
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#define HHI_MPEG_CLK_CNTL (0x05d << 2)
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#define HHI_VID_CLK_CNTL (0x05f << 2)
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#define HHI_TSIN_DEGLITCH_CLK_CNTL (0x060 << 2)
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#define HHI_TS_CLK_CNTL (0x064 << 2)
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#define HHI_VID_CLK_CNTL2 (0x065 << 2)
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#define HHI_MALI_CLK_CNTL (0x06c << 2)
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#define HHI_VPU_CLKC_CNTL (0x06d << 2)
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#define HHI_VPU_CLK_CNTL (0x06f << 2)
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#define HHI_HDMI_CLK_CNTL (0x073 << 2)
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#define HHI_DEMOD_CLK_CNTL (0x074 << 2)
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#define HHI_DEMOD_CLK_CNTL1 (0x075 << 2)
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#define HHI_ETH_CLK_CNTL (0x076 << 2)
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#define HHI_VDEC_CLK_CNTL (0x078 << 2)
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#define HHI_VDEC2_CLK_CNTL (0x079 << 2)
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#define HHI_VDEC3_CLK_CNTL (0x07a << 2)
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#define HHI_VDEC4_CLK_CNTL (0x07b << 2)
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#define HHI_HDMIRX_CLK_CNTL0 (0x07c << 2)
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#define HHI_VAPBCLK_CNTL (0x07d << 2)
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#define HHI_HDMIRX_CLK_CNTL1 (0x080 << 2)
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#define HHI_HDMIRX_CLK_CNTL2 (0x081 << 2)
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#define HHI_VPU_CLKB_CNTL (0x083 << 2)
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#define HHI_GEN_CLK_CNTL (0x08a << 2)
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#define HHI_AUDPLL_CLK_OUT_CNTL (0x08c << 2)
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#define HHI_HDMIRX_CLK_CNTL3 (0x08d << 2)
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#define HHI_VDIN_MEAS_CLK_CNTL (0x094 << 2)
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#define HHI_MIPIDSI_PHY_CLK_CNTL (0x095 << 2)
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#define HHI_NAND_CLK_CNTL (0x097 << 2)
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#define HHI_SD_EMMC_CLK_CNTL (0x099 << 2)
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#define HHI_TCON_CLK_CNTL (0x09c << 2)
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#define HHI_HDMI_AXI_CLK_CNTL (0x0b8 << 2)
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#define HHI_VID_LOCK_CLK_CNTL (0x0f2 << 2)
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#define HHI_ATV_DMD_SYS_CLK_CNTL (0x0f3 << 2)
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#define HHI_BT656_CLK_CNTL (0x0f5 << 2)
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#define HHI_CDAC_CLK_CNTL (0x0f6 << 2)
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#define HHI_SPICC_CLK_CNTL (0x0f7 << 2)
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/* HIU clk - Registers: 0xff63c000 */
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// APB4_DECODER_NON_SECURE_BASE 32'hFF63C000
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// APB4_DECODER_SECURE_BASE 32'hFF63C000
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//`define HHI_MIPI_CNTL0 8'h00
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//`define HHI_MIPI_CNTL1 8'h01
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//`define HHI_MIPI_CNTL2 8'h02
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//`define HHI_MIPI_STS 8'h03
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#define HHI_GP0_PLL_CNTL0 (0x010 << 2)
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#define HHI_GP0_PLL_CNTL1 (0x011 << 2)
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#define HHI_GP0_PLL_CNTL2 (0x012 << 2)
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#define HHI_GP0_PLL_CNTL3 (0x013 << 2)
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#define HHI_GP0_PLL_CNTL4 (0x014 << 2)
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#define HHI_GP0_PLL_CNTL5 (0x015 << 2)
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#define HHI_GP0_PLL_CNTL6 (0x016 << 2)
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#define HHI_GP0_PLL_STS (0x017 << 2)
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#define HHI_GP1_PLL_CNTL0 (0x018 << 2)
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#define HHI_GP1_PLL_CNTL1 (0x019 << 2)
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#define HHI_GP1_PLL_CNTL2 (0x01a << 2)
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#define HHI_GP1_PLL_CNTL3 (0x01b << 2)
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#define HHI_GP1_PLL_CNTL4 (0x01c << 2)
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#define HHI_GP1_PLL_CNTL5 (0x01d << 2)
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#define HHI_GP1_PLL_CNTL6 (0x01e << 2)
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#define HHI_GP1_PLL_STS (0x01f << 2)
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#define HHI_TCON_PLL_CNTL0 (0x020 << 2)
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#define HHI_TCON_PLL_CNTL1 (0x021 << 2)
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#define HHI_TCON_PLL_CNTL2 (0x022 << 2)
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#define HHI_TCON_PLL_CNTL3 (0x023 << 2)
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#define HHI_TCON_PLL_STS (0x024 << 2)
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//`define HHI_CADC_CNTL 8'h20
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//`define HHI_CADC_CNTL2 8'h21
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//`define HHI_CADC_CNTL3 8'h22
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//`define HHI_CADC_CNTL4 8'h23
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//`define HHI_CADC_CNTL5 8'h24
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//`define HHI_CADC_CNTL6 8'h25
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#define HHI_PCIE0_PLL_CNTL0 (0x025 << 2)
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#define HHI_PCIE0_PLL_CNTL1 (0x026 << 2)
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#define HHI_DADC_CNTL (0x027 << 2)
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#define HHI_DADC_CNTL2 (0x028 << 2)
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#define HHI_DADC_RDBK0_I (0x029 << 2)
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#define HHI_DADC_CNTL3 (0x02a << 2)
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#define HHI_DADC_CNTL4 (0x02b << 2)
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#define HHI_PCIE0_PLL_CNTL2 (0x02c << 2)
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#define HHI_PCIE0_PLL_CNTL3 (0x02d << 2)
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#define HHI_CVBS_DETECT_CNTL (0x02e << 2)
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#define HHI_XTAL_DIVN_CNTL (0x02f << 2)
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#define HHI_GCLK2_MPEG0 (0x030 << 2)
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#define HHI_GCLK2_MPEG1 (0x031 << 2)
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#define HHI_GCLK2_MPEG2 (0x032 << 2)
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#define HHI_GCLK2_OTHER (0x034 << 2)
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#define HHI_HIFI_PLL_CNTL0 (0x036 << 2)
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#define HHI_HIFI_PLL_CNTL1 (0x037 << 2)
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#define HHI_HIFI_PLL_CNTL2 (0x038 << 2)
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#define HHI_HIFI_PLL_CNTL3 (0x039 << 2)
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#define HHI_HIFI_PLL_CNTL4 (0x03a << 2)
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#define HHI_HIFI_PLL_CNTL5 (0x03b << 2)
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#define HHI_HIFI_PLL_CNTL6 (0x03c << 2)
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#define HHI_HIFI_PLL_STS (0x03d << 2)
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#define HHI_TIMER90K (0x03f << 2)
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#define HHI_MEM_PD_REG0 (0x040 << 2)
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#define HHI_S2_DADC_CNTL (0x041 << 2)
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#define HHI_S2_DADC_CNTL2 (0x042 << 2)
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#define HHI_VPU_MEM_PD_REG2 (0x04d << 2)
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#define HHI_GCLK_LOCK (0x04f << 2)
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#define HHI_GCLK_MPEG0 (0x050 << 2)
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#define HHI_GCLK_MPEG1 (0x051 << 2)
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#define HHI_GCLK_MPEG2 (0x052 << 2)
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#define HHI_GCLK_OTHER (0x054 << 2)
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#define HHI_GCLK_SP_MPEG (0x055 << 2)
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#define HHI_SYS_CPU_CLK_CNTL1 (0x057 << 2)
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#define HHI_SYS_CPU_RESET_CNTL (0x058 << 2)
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#define HHI_PCIE0_PLL_CNTL4 (0x05a << 2)
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#define HHI_PCIE0_PLL_CNTL5 (0x05b << 2)
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#define HHI_PCIE0_PLL_STS (0x05c << 2)
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#define HHI_HIFI1_PLL_CNTL0 (0x060 << 2)
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#define HHI_HIFI1_PLL_CNTL1 (0x061 << 2)
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#define HHI_HIFI1_PLL_CNTL2 (0x062 << 2)
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#define HHI_HIFI1_PLL_CNTL3 (0x063 << 2)
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#define HHI_HIFI1_PLL_STS (0x064 << 2)
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#define HHI_SYS_CPU_CLK_CNTL (0x067 << 2)
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#define HHI_VID_PLL_CLK_DIV (0x068 << 2)
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#define HHI_VIPNANOQ_CNTL (0x071 << 2)
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#define HHI_VIPNANOQ_CLK_CNTL (0x072 << 2)
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#define HHI_SYS_CPU_CLK_CNTL2 (0x084 << 2)
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#define HHI_SYS_CPU_CLK_CNTL3 (0x085 << 2)
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#define HHI_SYS_CPU_CLK_CNTL4 (0x086 << 2)
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#define HHI_SYS_CPU_CLK_CNTL5 (0x087 << 2)
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#define HHI_SYS_CPU_CLK_CNTL6 (0x088 << 2)
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#define HHI_DIF_CSI_PHY_CNTL10 (0x08e << 2)
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#define HHI_DIF_CSI_PHY_CNTL11 (0x08f << 2)
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#define HHI_DIF_CSI_PHY_CNTL12 (0x090 << 2)
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#define HHI_DIF_CSI_PHY_CNTL13 (0x091 << 2)
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#define HHI_DIF_CSI_PHY_CNTL14 (0x092 << 2)
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#define HHI_DIF_CSI_PHY_CNTL15 (0x093 << 2)
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#define HHI_LVDS_TX_PHY_CNTL0 (0x09a << 2)
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#define HHI_LVDS_TX_PHY_CNTL1 (0x09b << 2)
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#define HHI_FIX_PLL_CNTL0 (0x0a8 << 2)
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#define HHI_FIX_PLL_CNTL1 (0x0a9 << 2)
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#define HHI_FIX_PLL_CNTL2 (0x0aa << 2)
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#define HHI_FIX_PLL_CNTL3 (0x0ab << 2)
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#define HHI_FIX_PLL_CNTL4 (0x0ac << 2)
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#define HHI_FIX_PLL_CNTL5 (0x0ad << 2)
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#define HHI_FIX_PLL_CNTL6 (0x0ae << 2)
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#define HHI_FIX_PLL_STS (0x0af << 2)
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#define HHI_ADC_PLL_CNTL (0x0b0 << 2)
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#define HHI_ADC_PLL_CNTL1 (0x0b1 << 2)
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#define HHI_ADC_PLL_CNTL2 (0x0b2 << 2)
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#define HHI_ADC_PLL_CNTL3 (0x0b3 << 2)
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#define HHI_ADC_PLL_CNTL4 (0x0b4 << 2)
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#define HHI_ADC_PLL_CNTL5 (0x0b5 << 2)
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#define HHI_ADC_PLL_CNTL6 (0x0b6 << 2)
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#define HHI_ADC_PLL_STS (0x0b7 << 2)
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#define HHI_VDAC_CNTL0 (0x0bb << 2)
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#define HHI_VDAC_CNTL1 (0x0bc << 2)
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#define HHI_SYS_PLL_CNTL0 (0x0bd << 2)
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#define HHI_SYS_PLL_CNTL1 (0x0be << 2)
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#define HHI_SYS_PLL_CNTL2 (0x0bf << 2)
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#define HHI_SYS_PLL_CNTL3 (0x0c0 << 2)
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#define HHI_HDMI_PLL_CNTL0 (0x0c8 << 2)
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#define HHI_HDMI_PLL_CNTL1 (0x0c9 << 2)
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#define HHI_HDMI_PLL_CNTL2 (0x0ca << 2)
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#define HHI_HDMI_PLL_CNTL3 (0x0cb << 2)
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#define HHI_HDMI_PLL_CNTL4 (0x0cc << 2)
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#define HHI_HDMI_PLL_CNTL5 (0x0cd << 2)
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#define HHI_HDMI_PLL_CNTL6 (0x0ce << 2)
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#define HHI_HDMI_PLL_STS (0x0cf << 2)
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#define HHI_HDMI_PLL_VLOCK_CNTL (0x0d1 << 2)
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#define HHI_DIF_CSI_PHY_CNTL1 (0x0d9 << 2)
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#define HHI_DIF_CSI_PHY_CNTL2 (0x0da << 2)
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#define HHI_DIF_CSI_PHY_CNTL3 (0x0db << 2)
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#define HHI_DIF_CSI_PHY_CNTL16 (0x0de << 2)
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#define HHI_TCON_PLL_CNTL4 (0x0df << 2)
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#define HHI_TCON_PLL_CNTL5 (0x0e0 << 2)
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#define HHI_TCON_PLL_CNTL6 (0x0e1 << 2)
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#define HHI_HDMIRX_ARC_CNTL (0x0e8 << 2)
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#define HHI_DIF_CSI_PHY_CNTL4 (0x0e9 << 2)
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#define HHI_DIF_CSI_PHY_CNTL6 (0x0ea << 2)
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#define HHI_DIF_CSI_PHY_CNTL7 (0x0eb << 2)
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#define HHI_DIF_CSI_PHY_CNTL8 (0x0ec << 2)
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#define HHI_DIF_CSI_PHY_CNTL9 (0x0ed << 2)
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#define HHI_AXI_PIPEL_CNTL2 (0x0f0 << 2)
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#define HHI_AXI_PIPEL_CNTL (0x0f4 << 2)
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#define HHI_HDMIRX_AUD_PLL_CNTL (0x0f8 << 2)
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#define HHI_HDMIRX_AUD_PLL_CNTL2 (0x0f9 << 2)
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#define HHI_HDMIRX_AUD_PLL_CNTL3 (0x0fa << 2)
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#define HHI_AXI_PIPEL_CNTL1 (0x0fb << 2)
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#define HHI_DSP_CLK_CNTL (0x0fc << 2)
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#define HHI_HDMIRX_AUD_PLL_CNTL_I (0x0fe << 2)
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#endif /* __TXHD2_H */
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