115 lines
4.6 KiB
C
115 lines
4.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __T6D_H
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#define __T6D_H
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/* basic clk: 0xfe000000 */
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#define CLKCTRL_OSCIN_CTRL (0x01 << 2)
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#define CLKCTRL_RTC_BY_OSCIN_CTRL0 (0x02 << 2)
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#define CLKCTRL_RTC_BY_OSCIN_CTRL1 (0x03 << 2)
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#define CLKCTRL_RTC_CTRL (0x04 << 2)
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#define CLKCTRL_CHECK_CLK_RESULT (0x05 << 2)
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#define CLKCTRL_MBIST_ATSPEED_CTRL (0x06 << 2)
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#define CLKCTRL_LOCK_BIT_REG0 (0x08 << 2)
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#define CLKCTRL_LOCK_BIT_REG1 (0x09 << 2)
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#define CLKCTRL_LOCK_BIT_REG2 (0x0a << 2)
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#define CLKCTRL_LOCK_BIT_REG3 (0x0b << 2)
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#define CLKCTRL_PROT_BIT_REG0 (0x0c << 2)
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#define CLKCTRL_PROT_BIT_REG1 (0x0d << 2)
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#define CLKCTRL_PROT_BIT_REG2 (0x0e << 2)
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#define CLKCTRL_PROT_BIT_REG3 (0x0f << 2)
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#define CLKCTRL_SYS_CLK_CTRL0 (0x10 << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG0 (0x11 << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG1 (0x12 << 2)
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#define CLKCTRL_SYS_CLK_VPU_EN0 (0x19 << 2)
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#define CLKCTRL_SYS_CLK_VPU_EN1 (0x1a << 2)
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#define CLKCTRL_AXI_CLK_CTRL0 (0x1b << 2)
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#define CLKCTRL_TST_CTRL0 (0x20 << 2)
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#define CLKCTRL_TST_CTRL1 (0x21 << 2)
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#define CLKCTRL_CECB_CTRL0 (0x24 << 2)
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#define CLKCTRL_CECB_CTRL1 (0x25 << 2)
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#define CLKCTRL_SC_CLK_CTRL (0x26 << 2)
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#define CLKCTRL_CLK12_24_CTRL (0x2a << 2)
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#define CLKCTRL_VID_CLK0_CTRL (0x30 << 2)
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#define CLKCTRL_VID_CLK0_CTRL2 (0x31 << 2)
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#define CLKCTRL_VID_CLK0_DIV (0x32 << 2)
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#define CLKCTRL_VIID_CLK0_DIV (0x33 << 2)
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#define CLKCTRL_VIID_CLK0_CTRL (0x34 << 2)
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#define CLKCTRL_ENC0_HDMI_CLK_CTRL (0x35 << 2)
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#define CLKCTRL_HDMI_CLK_CTRL (0x38 << 2)
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#define CLKCTRL_VID_PLL_CLK0_DIV (0x39 << 2)
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#define CLKCTRL_VPU_CLK_CTRL (0x3a << 2)
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#define CLKCTRL_VPU_CLKB_CTRL (0x3b << 2)
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#define CLKCTRL_VID_LOCK_CLK_CTRL (0x3d << 2)
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#define CLKCTRL_VDIN_MEAS_CLK_CTRL (0x3e << 2)
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#define CLKCTRL_VAPBCLK_CTRL (0x3f << 2)
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#define CLKCTRL_AMFC_CLK_CTRL (0x40 << 2)
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#define CLKCTRL_CDAC_CLK_CTRL (0x42 << 2)
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#define CLKCTRL_HTX_CLK_CTRL0 (0x47 << 2)
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#define CLKCTRL_HTX_CLK_CTRL1 (0x48 << 2)
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#define CLKCTRL_HRX_CLK_CTRL0 (0x4a << 2)
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#define CLKCTRL_HRX_CLK_CTRL1 (0x4b << 2)
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#define CLKCTRL_HRX_CLK_CTRL2 (0x4c << 2)
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#define CLKCTRL_HRX_CLK_CTRL3 (0x4d << 2)
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#define CLKCTRL_VDEC2_CLK_CTRL (0x51 << 2)
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#define CLKCTRL_VDEC4_CLK_CTRL (0x53 << 2)
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#define CLKCTRL_TS_CLK_CTRL (0x56 << 2)
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#define CLKCTRL_MALI_CLK_CTRL (0x57 << 2)
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#define CLKCTRL_ETH_CLK_CTRL (0x59 << 2)
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#define CLKCTRL_NAND_CLK_CTRL (0x5a << 2)
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#define CLKCTRL_SPICC_CLK_CTRL (0x5d << 2)
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#define CLKCTRL_GEN_CLK_CTRL (0x5e << 2)
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#define CLKCTRL_SAR_CLK_CTRL0 (0x5f << 2)
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#define CLKCTRL_PWM_CLK_AB_CTRL (0x60 << 2)
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#define CLKCTRL_PWM_CLK_CD_CTRL (0x61 << 2)
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#define CLKCTRL_PWM_CLK_EF_CTRL (0x62 << 2)
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#define CLKCTRL_PWM_CLK_GH_CTRL (0x63 << 2)
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#define CLKCTRL_VID_PLL_CLK1_DIV (0x7d << 2)
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#define CLKCTRL_VID_PLL_CLK2_DIV (0x7e << 2)
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#define CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL (0x80 << 2)
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#define CLKCTRL_HDMI_VID_PLL_CLK_DIV (0x81 << 2)
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#define CLKCTRL_DEMOD_CLK_CNTL (0x82 << 2)
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#define CLKCTRL_DEMOD_CLK_CNTL1 (0x83 << 2)
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#define CLKCTRL_DEMOD_32K_CNTL0 (0x84 << 2)
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#define CLKCTRL_DEMOD_32K_CNTL1 (0x85 << 2)
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#define CLKCTRL_ATV_DMD_SYS_CLK_CNTL (0x86 << 2)
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#define CLKCTRL_TCON_CLK_CNTL (0x87 << 2)
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#define CLKCTRL_TSIN_CLK_CNTL (0x8c << 2)
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#define CLKCTRL_CLK81_GATE_CTRL_SYSWRAPPER (0x8d << 2)
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#define CLKCTRL_CLK81_GATE_CTRL_PERIPH (0x8e << 2)
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#define CLKCTRL_USB_CLK_CTRL0 (0x8f << 2)
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#define CLKCTRL_USB_CLK_CTRL1 (0x90 << 2)
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/* ANA_CTRL - Registers
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* REG_BASE: REGISTER_BASE_ADDR = 0xfe008000
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*/
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#define ANACTRL_SYS0PLL_CTRL0 (0x00 << 2)
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#define ANACTRL_SYS0PLL_CTRL1 (0x01 << 2)
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#define ANACTRL_SYS0PLL_STS (0x04 << 2)
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#define ANACTRL_FIXPLL_CTRL0 (0x10 << 2)
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#define ANACTRL_FIXPLL_CTRL1 (0x11 << 2)
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#define ANACTRL_FIXPLL_STS (0x17 << 2)
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#define ANACTRL_GP0PLL_CTRL0 (0x20 << 2)
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#define ANACTRL_GP0PLL_CTRL1 (0x21 << 2)
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#define ANACTRL_GP0PLL_CTRL2 (0x22 << 2)
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#define ANACTRL_GP0PLL_CTRL3 (0x23 << 2)
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#define ANACTRL_GP0PLL_STS (0x27 << 2)
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#define ANACTRL_HIFIPLL_CTRL0 (0x40 << 2)
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#define ANACTRL_HIFIPLL_CTRL1 (0x41 << 2)
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#define ANACTRL_HIFIPLL_CTRL2 (0x42 << 2)
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#define ANACTRL_HIFIPLL_CTRL3 (0x43 << 2)
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#define ANACTRL_HIFIPLL_STS (0x47 << 2)
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#define ANACTRL_HIFI1PLL_CTRL0 (0x30 << 2)
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#define ANACTRL_HIFI1PLL_CTRL1 (0x31 << 2)
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#define ANACTRL_HIFI1PLL_CTRL2 (0x32 << 2)
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#define ANACTRL_HIFI1PLL_CTRL3 (0x33 << 2)
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#define ANACTRL_HIFI1PLL_STS (0x37 << 2)
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#define ANACTRL_USBPLL_CTRL0 (0x50 << 2)
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#define ANACTRL_USBPLL_CTRL1 (0x51 << 2)
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#define ANACTRL_USBPLL_STS (0x54 << 2)
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#endif /* __T6D_H */
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