87 lines
5.0 KiB
C
87 lines
5.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __SC2_H
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#define __SC2_H
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#define ANACTRL_FIXPLL_CTRL1 (0x0011 << 2)
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#define ANACTRL_GP0PLL_CTRL0 (0x0020 << 2)
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#define ANACTRL_GP0PLL_CTRL1 (0x0021 << 2)
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#define ANACTRL_GP0PLL_CTRL2 (0x0022 << 2)
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#define ANACTRL_GP0PLL_CTRL3 (0x0023 << 2)
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#define ANACTRL_GP0PLL_CTRL4 (0x0024 << 2)
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#define ANACTRL_GP0PLL_CTRL5 (0x0025 << 2)
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#define ANACTRL_GP0PLL_CTRL6 (0x0026 << 2)
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#define ANACTRL_HIFIPLL_CTRL0 (0x0040 << 2)
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#define ANACTRL_HIFIPLL_CTRL1 (0x0041 << 2)
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#define ANACTRL_HIFIPLL_CTRL2 (0x0042 << 2)
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#define ANACTRL_HIFIPLL_CTRL3 (0x0043 << 2)
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#define ANACTRL_HIFIPLL_CTRL4 (0x0044 << 2)
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#define ANACTRL_HIFIPLL_CTRL5 (0x0045 << 2)
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#define ANACTRL_HIFIPLL_CTRL6 (0x0046 << 2)
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#define ANACTRL_PCIEPLL_CTRL0 (0x0050 << 2)
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#define ANACTRL_PCIEPLL_CTRL1 (0x0051 << 2)
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#define ANACTRL_PCIEPLL_CTRL2 (0x0052 << 2)
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#define ANACTRL_PCIEPLL_CTRL3 (0x0053 << 2)
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#define ANACTRL_PCIEPLL_CTRL4 (0x0054 << 2)
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#define ANACTRL_PCIEPLL_CTRL5 (0x0055 << 2)
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#define ANACTRL_MPLL_CTRL0 (0x0060 << 2)
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#define ANACTRL_MPLL_CTRL1 (0x0061 << 2)
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#define ANACTRL_MPLL_CTRL2 (0x0062 << 2)
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#define ANACTRL_MPLL_CTRL3 (0x0063 << 2)
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#define ANACTRL_MPLL_CTRL4 (0x0064 << 2)
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#define ANACTRL_MPLL_CTRL5 (0x0065 << 2)
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#define ANACTRL_MPLL_CTRL6 (0x0066 << 2)
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#define ANACTRL_MPLL_CTRL7 (0x0067 << 2)
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#define ANACTRL_MPLL_CTRL8 (0x0068 << 2)
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#define ANACTRL_HDMIPLL_CTRL0 (0x0070 << 2)
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#define CLKCTRL_RTC_BY_OSCIN_CTRL0 (0x0002 << 2)
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#define CLKCTRL_RTC_BY_OSCIN_CTRL1 (0x0003 << 2)
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#define CLKCTRL_RTC_CTRL (0x0004 << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG0 (0x0011 << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG1 (0x0012 << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG2 (0x0013 << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG3 (0x0014 << 2)
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#define CLKCTRL_CECA_CTRL0 (0x0022 << 2)
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#define CLKCTRL_CECA_CTRL1 (0x0023 << 2)
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#define CLKCTRL_CECB_CTRL0 (0x0024 << 2)
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#define CLKCTRL_CECB_CTRL1 (0x0025 << 2)
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#define CLKCTRL_SC_CLK_CTRL (0x0026 << 2)
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#define CLKCTRL_DSPA_CLK_CTRL0 (0x0027 << 2)
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#define CLKCTRL_CLK12_24_CTRL (0x002a << 2)
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#define CLKCTRL_VID_CLK_CTRL (0x0030 << 2)
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#define CLKCTRL_VID_CLK_CTRL2 (0x0031 << 2)
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#define CLKCTRL_VID_CLK_DIV (0x0032 << 2)
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#define CLKCTRL_VIID_CLK_DIV (0x0033 << 2)
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#define CLKCTRL_VIID_CLK_CTRL (0x0034 << 2)
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#define CLKCTRL_HDMI_CLK_CTRL (0x0038 << 2)
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#define CLKCTRL_VPU_CLK_CTRL (0x003a << 2)
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#define CLKCTRL_VPU_CLKB_CTRL (0x003b << 2)
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#define CLKCTRL_VPU_CLKC_CTRL (0x003c << 2)
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#define CLKCTRL_VID_LOCK_CLK_CTRL (0x003d << 2)
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#define CLKCTRL_VDIN_MEAS_CLK_CTRL (0x003e << 2)
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#define CLKCTRL_VAPBCLK_CTRL (0x003f << 2)
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#define CLKCTRL_VDEC_CLK_CTRL (0x0050 << 2)
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#define CLKCTRL_VDEC2_CLK_CTRL (0x0051 << 2)
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#define CLKCTRL_VDEC3_CLK_CTRL (0x0052 << 2)
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#define CLKCTRL_VDEC4_CLK_CTRL (0x0053 << 2)
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#define CLKCTRL_WAVE420L_CLK_CTRL (0x0054 << 2)
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#define CLKCTRL_WAVE420L_CLK_CTRL2 (0x0055 << 2)
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#define CLKCTRL_TS_CLK_CTRL (0x0056 << 2)
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#define CLKCTRL_MALI_CLK_CTRL (0x0057 << 2)
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#define CLKCTRL_NAND_CLK_CTRL (0x005a << 2)
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#define CLKCTRL_SD_EMMC_CLK_CTRL (0x005b << 2)
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#define CLKCTRL_SPICC_CLK_CTRL (0x005d << 2)
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#define CLKCTRL_GEN_CLK_CTRL (0x005e << 2)
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#define CLKCTRL_SAR_CLK_CTRL0 (0x005f << 2)
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#define CLKCTRL_PWM_CLK_AB_CTRL (0x0060 << 2)
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#define CLKCTRL_PWM_CLK_CD_CTRL (0x0061 << 2)
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#define CLKCTRL_PWM_CLK_EF_CTRL (0x0062 << 2)
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#define CLKCTRL_PWM_CLK_GH_CTRL (0x0063 << 2)
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#define CLKCTRL_PWM_CLK_IJ_CTRL (0x0064 << 2)
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#endif /* __SC2_H */
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