502 lines
14 KiB
C
502 lines
14 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#ifdef CONFIG_AMLOGIC_CLK_DEBUG
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#include <linux/clkdev.h>
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#endif
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include "meson-clkc-utils.h"
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#include "clk-regmap.h"
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#include "c5.h"
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#include <dt-bindings/clock/amlogic,c5-clkc.h>
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static struct clk_regmap osc_32m_en = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = RTCCTRL_REG_CTRL0,
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.bit_idx = 16,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "osc_32m_en",
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.ops = &clk_regmap_gate_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "osc_32m"
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap ao_rough_32k_div = {
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.data = &(struct clk_regmap_div_data) {
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.offset = AO_CLKCTRL_ROUGH_32K_CTRL,
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.shift = 0,
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.width = 20,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_rough_32k_div",
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.ops = &clk_regmap_divider_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&osc_32m_en.hw,
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap ao_rough_32k = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = AO_CLKCTRL_ROUGH_32K_CTRL,
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.bit_idx = 20,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_rough_32k",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&ao_rough_32k_div.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static const struct clk_parent_data ao_oscin32k_clk_parent_data[] = {
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{ .hw = &ao_rough_32k.hw },
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{ .fw_name = "xtal_32k" }
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};
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static struct clk_regmap ao_oscin32k_clk = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CLKCTRL_OSCIN_CTRL,
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.mask = 0x1,
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.shift = 2,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_oscin32k_clk",
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.ops = &clk_regmap_mux_ops,
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.parent_data = ao_oscin32k_clk_parent_data,
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.num_parents = ARRAY_SIZE(ao_oscin32k_clk_parent_data),
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},
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};
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static const struct clk_parent_data ao_oscin_clk_parent_data[] = {
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{ .fw_name = "xtal" },
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{ .hw = &ao_oscin32k_clk.hw }
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};
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static struct clk_regmap ao_oscin_clk = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CLKCTRL_OSCIN_CTRL,
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.mask = 0x1,
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.shift = 1,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_oscin_clk",
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.ops = &clk_regmap_mux_ops,
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.parent_data = ao_oscin_clk_parent_data,
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.num_parents = ARRAY_SIZE(ao_oscin_clk_parent_data),
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},
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};
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static const struct clk_parent_data ao_sys_clk_parent_data[] = {
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{ .fw_name = "sys_clk" },
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{ .hw = &ao_oscin_clk.hw }
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};
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static struct clk_regmap ao_sys_clk = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CLKCTRL_OSCIN_CTRL,
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.mask = 0x1,
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.shift = 0,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_sys_clk",
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.ops = &clk_regmap_mux_ops,
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.parent_data = ao_sys_clk_parent_data,
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.num_parents = ARRAY_SIZE(ao_sys_clk_parent_data),
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},
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};
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static const struct clk_parent_data ao_psram_parent_data[] = {
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{ .hw = &ao_oscin_clk.hw },
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{ .fw_name = "fclk_div5" },
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{ .fw_name = "fclk_div4" },
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{ .fw_name = "fclk_div3" }
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};
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static struct clk_regmap ao_psram_mux = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CLKCTRL_PSRAM_CLK_CTRL,
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.mask = 0x3,
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.shift = 9,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_psram_mux",
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.ops = &clk_regmap_mux_ops,
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.parent_data = ao_psram_parent_data,
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.num_parents = ARRAY_SIZE(ao_psram_parent_data),
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},
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};
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static struct clk_regmap ao_psram_div = {
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.data = &(struct clk_regmap_div_data) {
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.offset = AO_CLKCTRL_PSRAM_CLK_CTRL,
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.shift = 0,
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.width = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_psram_div",
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.ops = &clk_regmap_divider_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&ao_psram_mux.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_psram = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = AO_CLKCTRL_PSRAM_CLK_CTRL,
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.bit_idx = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_psram",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&ao_psram_div.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT |
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CLK_IGNORE_UNUSED,
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},
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};
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static const struct clk_parent_data ao_pwm_parent_data[] = {
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{ .hw = &ao_oscin_clk.hw },
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{ .hw = &ao_sys_clk.hw },
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{ .hw = &ao_oscin32k_clk.hw },
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{ .fw_name = "fclk_div5" }
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};
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static struct clk_regmap ao_pwm_a_mux = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CLKCTRL_PWM_CLK_A_CTRL,
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.mask = 0x3,
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.shift = 9,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_pwm_a_mux",
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.ops = &clk_regmap_mux_ops,
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.parent_data = ao_pwm_parent_data,
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.num_parents = ARRAY_SIZE(ao_pwm_parent_data),
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},
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};
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static struct clk_regmap ao_pwm_a_div = {
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.data = &(struct clk_regmap_div_data) {
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.offset = AO_CLKCTRL_PWM_CLK_A_CTRL,
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.shift = 0,
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.width = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_pwm_a_div",
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.ops = &clk_regmap_divider_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&ao_pwm_a_mux.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_pwm_a = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = AO_CLKCTRL_PWM_CLK_A_CTRL,
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.bit_idx = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_pwm_a",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&ao_pwm_a_div.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_pwm_b_mux = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CLKCTRL_PWM_CLK_B_CTRL,
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.mask = 0x3,
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.shift = 9,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_pwm_b_mux",
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.ops = &clk_regmap_mux_ops,
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.parent_data = ao_pwm_parent_data,
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.num_parents = ARRAY_SIZE(ao_pwm_parent_data),
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},
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};
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static struct clk_regmap ao_pwm_b_div = {
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.data = &(struct clk_regmap_div_data) {
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.offset = AO_CLKCTRL_PWM_CLK_B_CTRL,
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.shift = 0,
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.width = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_pwm_b_div",
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.ops = &clk_regmap_divider_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&ao_pwm_b_mux.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_pwm_b = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = AO_CLKCTRL_PWM_CLK_B_CTRL,
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.bit_idx = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_pwm_b",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&ao_pwm_b_div.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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#define MESON_CLK_GATE_AO_SYS_CLK(_name, _reg, _bit) \
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static struct clk_regmap _name = { \
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.data = &(struct clk_regmap_gate_data) { \
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.offset = (_reg), \
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.bit_idx = (_bit), \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name, \
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.ops = &clk_regmap_gate_ops, \
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.parent_hws = (const struct clk_hw *[]) { \
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&ao_sys_clk.hw, \
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}, \
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.num_parents = 1, \
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.flags = CLK_IGNORE_UNUSED, \
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}, \
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}
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_rtc_reg, AO_CLKCTRL_RTC_SYS_CLK0, 1);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_clktree, AO_CLKCTRL_RTC_SYS_CLK0, 2);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_rst_ctrl, AO_CLKCTRL_RTC_SYS_CLK0, 3);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_clk_pad, AO_CLKCTRL_RTC_SYS_CLK0, 4);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_rtc_dig, AO_CLKCTRL_RTC_SYS_CLK0, 5);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_irq, AO_CLKCTRL_RTC_SYS_CLK0, 6);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_pwrctrl, AO_CLKCTRL_RTC_SYS_CLK0, 7);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_pwm_a, AO_CLKCTRL_RTC_SYS_CLK0, 8);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_pwm_b, AO_CLKCTRL_RTC_SYS_CLK0, 9);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_i3c, AO_CLKCTRL_RTC_SYS_CLK0, 10);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_spisg0, AO_CLKCTRL_RTC_SYS_CLK0, 11);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_ir_ctrl, AO_CLKCTRL_RTC_SYS_CLK0, 12);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_i2c_m_a, AO_CLKCTRL_RTC_SYS_CLK0, 15);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_i2c_m_b, AO_CLKCTRL_RTC_SYS_CLK0, 16);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_sed, AO_CLKCTRL_RTC_SYS_CLK0, 19);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_uart_a, AO_CLKCTRL_RTC_SYS_CLK0, 20);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_uart_b, AO_CLKCTRL_RTC_SYS_CLK0, 21);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_ao_spi, AO_CLKCTRL_RTC_SYS_CLK0, 25);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_rtc_secure, AO_CLKCTRL_RTC_SYS_CLK0, 26);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_ao_isp, AO_CLKCTRL_RTC_SYS_CLK0, 27);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_aocpu, AO_CLKCTRL_RTC_SYS_CLK0, 28);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_sram, AO_CLKCTRL_RTC_SYS_CLK0, 29);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_psram_apb, AO_CLKCTRL_RTC_SYS_CLK0, 30);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_psram_axi, AO_CLKCTRL_RTC_SYS_CLK0, 31);
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static struct clk_regmap *const aoclk_regmaps[] = {
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&ao_rough_32k_div,
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&ao_rough_32k,
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&ao_oscin32k_clk,
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&ao_oscin_clk,
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&ao_sys_clk,
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&ao_psram_mux,
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&ao_psram_div,
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&ao_psram,
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&ao_pwm_a_mux,
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&ao_pwm_a_div,
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&ao_pwm_a,
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&ao_pwm_b_mux,
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&ao_pwm_b_div,
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&ao_pwm_b,
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&ao_sys_rtc_reg,
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&ao_sys_clktree,
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&ao_sys_rst_ctrl,
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&ao_sys_clk_pad,
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&ao_sys_rtc_dig,
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&ao_sys_irq,
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&ao_sys_pwrctrl,
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&ao_sys_pwm_a,
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&ao_sys_pwm_b,
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&ao_sys_i3c,
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&ao_sys_spisg0,
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&ao_sys_ir_ctrl,
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&ao_sys_i2c_m_a,
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&ao_sys_i2c_m_b,
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&ao_sys_sed,
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&ao_sys_uart_a,
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&ao_sys_uart_b,
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&ao_sys_ao_spi,
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&ao_sys_rtc_secure,
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&ao_sys_ao_isp,
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&ao_sys_aocpu,
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&ao_sys_sram,
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&ao_sys_psram_apb,
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&ao_sys_psram_axi
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};
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static struct clk_regmap *const rtc_regmap[] = {
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&osc_32m_en
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};
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static struct clk_hw *c5_aoclk_hw_clks[] = {
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[CLKID_OSC_32M_EN] = &osc_32m_en.hw,
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[CLKID_AO_ROUGH_32K_DIV] = &ao_rough_32k_div.hw,
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[CLKID_AO_ROUGH_32K] = &ao_rough_32k.hw,
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[CLKID_AO_OSCIN32K_CLK] = &ao_oscin32k_clk.hw,
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[CLKID_AO_OSCIN_CLK] = &ao_oscin_clk.hw,
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[CLKID_AO_SYS_CLK] = &ao_sys_clk.hw,
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[CLKID_AO_PSRAM_MUX] = &ao_psram_mux.hw,
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[CLKID_AO_PSRAM_DIV] = &ao_psram_div.hw,
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[CLKID_AO_PSRAM] = &ao_psram.hw,
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[CLKID_AO_PWM_A_MUX] = &ao_pwm_a_mux.hw,
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[CLKID_AO_PWM_A_DIV] = &ao_pwm_a_div.hw,
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[CLKID_AO_PWM_A] = &ao_pwm_a.hw,
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[CLKID_AO_PWM_B_MUX] = &ao_pwm_b_mux.hw,
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[CLKID_AO_PWM_B_DIV] = &ao_pwm_b_div.hw,
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[CLKID_AO_PWM_B] = &ao_pwm_b.hw,
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[CLKID_AO_SYS_RTC_REG] = &ao_sys_rtc_reg.hw,
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[CLKID_AO_SYS_CLKTREE] = &ao_sys_clktree.hw,
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[CLKID_AO_SYS_RST_CTRL] = &ao_sys_rst_ctrl.hw,
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[CLKID_AO_SYS_CLK_PAD] = &ao_sys_clk_pad.hw,
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[CLKID_AO_SYS_RTC_DIG] = &ao_sys_rtc_dig.hw,
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[CLKID_AO_SYS_IRQ] = &ao_sys_irq.hw,
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[CLKID_AO_SYS_PWRCTRL] = &ao_sys_pwrctrl.hw,
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[CLKID_AO_SYS_PWM_A] = &ao_sys_pwm_a.hw,
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[CLKID_AO_SYS_PWM_B] = &ao_sys_pwm_b.hw,
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[CLKID_AO_SYS_I3C] = &ao_sys_i3c.hw,
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[CLKID_AO_SYS_SPISG0] = &ao_sys_spisg0.hw,
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[CLKID_AO_SYS_IR_CTRL] = &ao_sys_ir_ctrl.hw,
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[CLKID_AO_SYS_I2C_M_A] = &ao_sys_i2c_m_a.hw,
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[CLKID_AO_SYS_I2C_M_B] = &ao_sys_i2c_m_b.hw,
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[CLKID_AO_SYS_SED] = &ao_sys_sed.hw,
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[CLKID_AO_SYS_UART_A] = &ao_sys_uart_a.hw,
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[CLKID_AO_SYS_UART_B] = &ao_sys_uart_b.hw,
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[CLKID_AO_SYS_AO_SPI] = &ao_sys_ao_spi.hw,
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[CLKID_AO_SYS_RTC_SECURE] = &ao_sys_rtc_secure.hw,
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[CLKID_AO_SYS_AO_ISP] = &ao_sys_ao_isp.hw,
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[CLKID_AO_SYS_AOCPU] = &ao_sys_aocpu.hw,
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[CLKID_AO_SYS_SRAM] = &ao_sys_sram.hw,
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[CLKID_AO_SYS_PSRAM_APB] = &ao_sys_psram_apb.hw,
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[CLKID_AO_SYS_PSRAM_AXI] = &ao_sys_psram_axi.hw
|
|
};
|
|
|
|
static const struct meson_clk_hw_data c5_aoclks = {
|
|
.hws = c5_aoclk_hw_clks,
|
|
.num = ARRAY_SIZE(c5_aoclk_hw_clks),
|
|
};
|
|
|
|
static int meson_c5_aoclk_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct regmap *basic_map;
|
|
struct regmap *rtc_map;
|
|
struct meson_clk_hw_data *data;
|
|
int ret, i;
|
|
|
|
data = (struct meson_clk_hw_data *)of_device_get_match_data(dev);
|
|
if (!data)
|
|
return -ENODEV;
|
|
|
|
basic_map = meson_clk_regmap_resource(pdev, dev, 0);
|
|
if (IS_ERR(basic_map)) {
|
|
dev_err(dev, "basic clk registers not found\n");
|
|
return PTR_ERR(basic_map);
|
|
}
|
|
|
|
rtc_map = meson_clk_regmap_resource(pdev, dev, 1);
|
|
if (IS_ERR(rtc_map)) {
|
|
dev_err(dev, "rtc clk registers not found\n");
|
|
return PTR_ERR(rtc_map);
|
|
}
|
|
|
|
/* Populate regmap for the regmap backed clocks */
|
|
for (i = 0; i < ARRAY_SIZE(aoclk_regmaps); i++)
|
|
aoclk_regmaps[i]->map = basic_map;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(rtc_regmap); i++)
|
|
rtc_regmap[i]->map = rtc_map;
|
|
|
|
for (i = 0; i < data->num; i++) {
|
|
/* array might be sparse */
|
|
if (!data->hws[i])
|
|
continue;
|
|
|
|
ret = devm_clk_hw_register(dev, data->hws[i]);
|
|
if (ret) {
|
|
dev_err(dev, "Clock registration failed\n");
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_AMLOGIC_CLK_DEBUG
|
|
ret = devm_clk_hw_register_clkdev(dev, data->hws[i],
|
|
NULL,
|
|
clk_hw_get_name(data->hws[i]));
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to clkdev register: %d\n", ret);
|
|
return ret;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,
|
|
(void *)data);
|
|
}
|
|
|
|
static const struct of_device_id clkc_match_table[] = {
|
|
{
|
|
.compatible = "amlogic,c5-aoclkc",
|
|
.data = &c5_aoclks
|
|
},
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver c5_aoclk_driver = {
|
|
.probe = meson_c5_aoclk_probe,
|
|
.driver = {
|
|
.name = "c5-aoclkc",
|
|
.of_match_table = clkc_match_table,
|
|
},
|
|
};
|
|
|
|
#ifdef CONFIG_AMLOGIC_MODIFY
|
|
int __init c5_aoclk_init(void)
|
|
{
|
|
return platform_driver_register(&c5_aoclk_driver);
|
|
}
|
|
|
|
void __exit c5_aoclk_exit(void)
|
|
{
|
|
platform_driver_unregister(&c5_aoclk_driver);
|
|
}
|
|
#else
|
|
builtin_platform_driver(c5_aoclk_driver);
|
|
MODULE_LICENSE("GPL v2");
|
|
#endif
|