372 lines
9.9 KiB
C
372 lines
9.9 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#ifdef CONFIG_AMLOGIC_CLK_DEBUG
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#include <linux/clkdev.h>
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#endif
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include "meson-clkc-utils.h"
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#include "clk-regmap.h"
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#include "c4.h"
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#include <dt-bindings/clock/amlogic,c4-clkc.h>
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static struct clk_regmap ao_rough_32k_clk_div = {
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.data = &(struct clk_regmap_div_data) {
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.offset = AO_CLKCTRL_ROUGH_32K_CTRL,
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.shift = 0,
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.width = 20,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_rough_32k_clk_div",
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.ops = &clk_regmap_divider_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "osc_32m"
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap ao_rough_32k_clk = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = AO_CLKCTRL_ROUGH_32K_CTRL,
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.bit_idx = 20,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_rough_32k_clk",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&ao_rough_32k_clk_div.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static const struct clk_parent_data ao_oscin32k_clk_parent_data[] = {
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{ .hw = &ao_rough_32k_clk.hw },
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{ .fw_name = "xtal_32k" }
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};
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static struct clk_regmap ao_oscin32k_clk = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CLKCTRL_OSCIN_CTRL,
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.mask = 0x3,
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.shift = 2,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_oscin32k_clk",
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.ops = &clk_regmap_mux_ops,
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.parent_data = ao_oscin32k_clk_parent_data,
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.num_parents = ARRAY_SIZE(ao_oscin32k_clk_parent_data),
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},
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};
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static const struct clk_parent_data ao_oscin_clk_parent_data[] = {
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{ .fw_name = "xtal" },
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{ .hw = &ao_oscin32k_clk.hw }
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};
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static struct clk_regmap ao_oscin_clk = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CLKCTRL_OSCIN_CTRL,
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.mask = 0x1,
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.shift = 1,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_oscin_clk",
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.ops = &clk_regmap_mux_ops,
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.parent_data = ao_oscin_clk_parent_data,
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.num_parents = ARRAY_SIZE(ao_oscin_clk_parent_data),
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},
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};
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static const struct clk_parent_data ao_sys_clk_parent_data[] = {
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{ .fw_name = "sys_clk" },
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{ .hw = &ao_oscin_clk.hw }
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};
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static struct clk_regmap ao_sys_clk = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CLKCTRL_OSCIN_CTRL,
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.mask = 0x1,
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.shift = 0,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_sys_clk",
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.ops = &clk_regmap_mux_ops,
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.parent_data = ao_sys_clk_parent_data,
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.num_parents = ARRAY_SIZE(ao_sys_clk_parent_data),
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},
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};
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static const struct clk_parent_data ao_pwm_parent_data[] = {
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{ .hw = &ao_oscin_clk.hw },
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{ .hw = &ao_sys_clk.hw },
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{ .hw = &ao_oscin32k_clk.hw },
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{ .fw_name = "xtal" }
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};
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static struct clk_regmap ao_pwm_j_mux = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CLKCTRL_PWM_CLK_JK_CTRL,
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.mask = 0x3,
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.shift = 9,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_pwm_j_mux",
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.ops = &clk_regmap_mux_ops,
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.parent_data = ao_pwm_parent_data,
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.num_parents = ARRAY_SIZE(ao_pwm_parent_data),
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},
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};
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static struct clk_regmap ao_pwm_j_div = {
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.data = &(struct clk_regmap_div_data) {
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.offset = AO_CLKCTRL_PWM_CLK_JK_CTRL,
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.shift = 0,
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.width = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_pwm_j_div",
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.ops = &clk_regmap_divider_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&ao_pwm_j_mux.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_pwm_j = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = AO_CLKCTRL_PWM_CLK_JK_CTRL,
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.bit_idx = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_pwm_j",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&ao_pwm_j_div.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_pwm_k_mux = {
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.data = &(struct clk_regmap_mux_data) {
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.offset = AO_CLKCTRL_PWM_CLK_JK_CTRL,
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.mask = 0x3,
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.shift = 25,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_pwm_k_mux",
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.ops = &clk_regmap_mux_ops,
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.parent_data = ao_pwm_parent_data,
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.num_parents = ARRAY_SIZE(ao_pwm_parent_data),
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},
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};
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static struct clk_regmap ao_pwm_k_div = {
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.data = &(struct clk_regmap_div_data) {
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.offset = AO_CLKCTRL_PWM_CLK_JK_CTRL,
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.shift = 16,
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.width = 8,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_pwm_k_div",
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.ops = &clk_regmap_divider_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&ao_pwm_k_mux.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap ao_pwm_k = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = AO_CLKCTRL_PWM_CLK_JK_CTRL,
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.bit_idx = 24,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "ao_pwm_k",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&ao_pwm_k_div.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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#define MESON_CLK_GATE_AO_SYS_CLK(_name, _reg, _bit) \
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struct clk_regmap _name = { \
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.data = &(struct clk_regmap_gate_data) { \
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.offset = (_reg), \
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.bit_idx = (_bit), \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name, \
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.ops = &clk_regmap_gate_ops, \
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.parent_hws = (const struct clk_hw *[]) { \
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&ao_sys_clk.hw, \
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}, \
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.num_parents = 1, \
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.flags = CLK_IGNORE_UNUSED, \
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}, \
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}
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_apb_clk, AO_CLKCTRL_RTC_SYS_CLK, 0);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_rtc_reg, AO_CLKCTRL_RTC_SYS_CLK, 1);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_rtc_clk, AO_CLKCTRL_RTC_SYS_CLK, 2);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_reset_ctrl, AO_CLKCTRL_RTC_SYS_CLK, 3);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_pad_ctrl, AO_CLKCTRL_RTC_SYS_CLK, 4);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_rtc_dig, AO_CLKCTRL_RTC_SYS_CLK, 5);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_irq_ctrl, AO_CLKCTRL_RTC_SYS_CLK, 6);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_pwr_ctrl, AO_CLKCTRL_RTC_SYS_CLK, 7);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_pwm_j, AO_CLKCTRL_RTC_SYS_CLK, 8);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_pwm_k, AO_CLKCTRL_RTC_SYS_CLK, 9);
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MESON_CLK_GATE_AO_SYS_CLK(ao_sys_sed, AO_CLKCTRL_RTC_SYS_CLK, 10);
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static struct clk_regmap *const aoclk_regmaps[] = {
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&ao_rough_32k_clk_div,
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&ao_rough_32k_clk,
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&ao_oscin32k_clk,
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&ao_oscin_clk,
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&ao_sys_clk,
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&ao_pwm_j_mux,
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&ao_pwm_j_div,
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&ao_pwm_j,
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&ao_pwm_k_mux,
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&ao_pwm_k_div,
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&ao_pwm_k,
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&ao_sys_apb_clk,
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&ao_sys_rtc_reg,
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&ao_sys_rtc_clk,
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&ao_sys_reset_ctrl,
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&ao_sys_pad_ctrl,
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&ao_sys_rtc_dig,
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&ao_sys_irq_ctrl,
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&ao_sys_pwr_ctrl,
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&ao_sys_pwm_j,
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&ao_sys_pwm_k,
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&ao_sys_sed
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};
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static struct clk_hw *c4_aoclk_hw_clks[] = {
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[CLKID_AO_ROUGH_32K_CLK_DIV] = &ao_rough_32k_clk_div.hw,
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[CLKID_AO_ROUGH_32K_CLK] = &ao_rough_32k_clk.hw,
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[CLKID_AO_OSCIN32K_CLK] = &ao_oscin32k_clk.hw,
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[CLKID_AO_OSCIN_CLK] = &ao_oscin_clk.hw,
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[CLKID_AO_SYS_CLK] = &ao_sys_clk.hw,
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[CLKID_AO_PWM_J_MUX] = &ao_pwm_j_mux.hw,
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[CLKID_AO_PWM_J_DIV] = &ao_pwm_j_div.hw,
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[CLKID_AO_PWM_J] = &ao_pwm_j.hw,
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[CLKID_AO_PWM_K_MUX] = &ao_pwm_k_mux.hw,
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[CLKID_AO_PWM_K_DIV] = &ao_pwm_k_div.hw,
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[CLKID_AO_PWM_K] = &ao_pwm_k.hw,
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[CLKID_AO_SYS_APB_CLK] = &ao_sys_apb_clk.hw,
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[CLKID_AO_SYS_RTC_REG] = &ao_sys_rtc_reg.hw,
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[CLKID_AO_SYS_RTC_CLK] = &ao_sys_rtc_clk.hw,
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[CLKID_AO_SYS_RESET_CTRL] = &ao_sys_reset_ctrl.hw,
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[CLKID_AO_SYS_PAD_CTRL] = &ao_sys_pad_ctrl.hw,
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[CLKID_AO_SYS_RTC_DIG] = &ao_sys_rtc_dig.hw,
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[CLKID_AO_SYS_IRQ_CTRL] = &ao_sys_irq_ctrl.hw,
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[CLKID_AO_SYS_PWR_CTRL] = &ao_sys_pwr_ctrl.hw,
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[CLKID_AO_SYS_PWM_J] = &ao_sys_pwm_j.hw,
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[CLKID_AO_SYS_PWM_K] = &ao_sys_pwm_k.hw,
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[CLKID_AO_SYS_SED] = &ao_sys_sed.hw
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};
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static const struct meson_clk_hw_data c4_aoclks = {
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.hws = c4_aoclk_hw_clks,
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.num = ARRAY_SIZE(c4_aoclk_hw_clks),
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};
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static int meson_c4_aoclk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct regmap *basic_map;
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struct meson_clk_hw_data *data;
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int ret, i;
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data = (struct meson_clk_hw_data *)of_device_get_match_data(dev);
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if (!data)
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return -ENODEV;
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basic_map = meson_clk_regmap_resource(pdev, dev, 0);
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if (IS_ERR(basic_map)) {
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dev_err(dev, "basic clk registers not found\n");
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return PTR_ERR(basic_map);
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}
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/* Populate regmap for the regmap backed clocks */
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for (i = 0; i < ARRAY_SIZE(aoclk_regmaps); i++)
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aoclk_regmaps[i]->map = basic_map;
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for (i = 0; i < data->num; i++) {
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/* array might be sparse */
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if (!data->hws[i])
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continue;
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ret = devm_clk_hw_register(dev, data->hws[i]);
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if (ret) {
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dev_err(dev, "Clock registration failed\n");
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return ret;
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}
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#ifdef CONFIG_AMLOGIC_CLK_DEBUG
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ret = devm_clk_hw_register_clkdev(dev, data->hws[i],
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NULL,
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clk_hw_get_name(data->hws[i]));
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if (ret < 0) {
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dev_err(dev, "Failed to clkdev register: %d\n", ret);
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return ret;
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}
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#endif
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}
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return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,
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(void *)data);
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}
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static const struct of_device_id clkc_match_table[] = {
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{
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.compatible = "amlogic,c4-aoclkc",
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.data = &c4_aoclks
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},
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{}
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};
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static struct platform_driver c4_aoclk_driver = {
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.probe = meson_c4_aoclk_probe,
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.driver = {
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.name = "c4-aoclkc",
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.of_match_table = clkc_match_table,
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},
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};
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#ifdef CONFIG_AMLOGIC_MODIFY
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int __init c4_aoclk_init(void)
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{
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return platform_driver_register(&c4_aoclk_driver);
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}
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void __exit c4_aoclk_exit(void)
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{
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platform_driver_unregister(&c4_aoclk_driver);
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}
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#else
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builtin_platform_driver(c4_aoclk_driver);
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MODULE_LICENSE("GPL v2");
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#endif
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